Instruction Manual

MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
24 ______________________________________________________________________________________
Figure 12. DRX Mode Sequence of the MAX1471
ADATA OR
FDATA
t
OFF
t
OFF
DIO
t
CPU
t
RF
CS
t
CPU
t
LOW
t
RF
Table 12. RF Settle Timer (t
RF
)
Configuration
TIME BASE
(1 LSB)
MIN t
RF
REG 0x7 = 0x00
REG 0x8 = 0x01
MAX t
RF
REG 0x7 = 0xFF
REG 0x8 = 0xFF
120µs 120µs 7.86s
Table 10. Off-Timer (t
OFF
) Configuration
PRESCALE1 PRESCALE0
t
OFF
TIME BASE
(1 LSB)
MIN t
OFF
REG 0x4 = 0x00
REG 0x5 = 0x01
MAX t
OFF
REG 0x4 = 0xFF
REG 0x5 = 0xFF
00120µs 120µs 7.86s
01480µs 480µs 31.46s
101920µs 1.92ms 2 min 6s
117680µs 7.68ms 8 min 23s
Table 11. CPU Recovery Timer (t
CPU
)
Configuration
TIME BASE
(1 LSB)
MIN t
CPU
REG 0x6 = 0x01
MAX t
CPU
REG 0x6 = 0xFF
120µs 120µs 30.72ms
Chip Information
TRANSISTOR COUNT: 21,344
PROCESS: CMOS