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General Description

The MAX1302/MAX1303 multirange, low-power, 16-bit,

successive-approximation, analog-to-digital converters

(ADCs) operate from a single +5V supply and achieve

throughput rates up to 115ksps. A separate digital sup-

ply allows digital interfacing with 2.7V to 5.25V systems

using the SPI™-/QSPI™-/MICROWIRE™-compatible

serial interface. Partial power-down mode reduces the

supply current to 1.3mA (typ). Full power-down mode

reduces the power-supply current to 1µA (typ).

The MAX1302 provides eight (single-ended) or four

(true differential) analog input channels. The MAX1303

provides four (single-ended) or two (true differential)

analog input channels. Each analog input channel is

independently software programmable for seven

single-ended input ranges (0 to +V

REF

/2, -V

REF

/2 to 0,

0 to +V

REF

, -V

REF

to 0, ±V

REF

/4, ±V

REF

/2, and ±V

REF

and three differential input ranges (±V

REF

/2, ±V

REF

±2 x V

REF

An on-chip +4.096V reference offers a small convenient

ADC solution. The MAX1302/MAX1303 also accept an

external reference voltage between 3.800V and 4.136V.

The MAX1302 is available in a 24-pin TSSOP package

and the MAX1303 is available in a 20-pin TSSOP pack-

age. Each device is specified for operation from -40°C

to +85°C.

Applications

Industrial Control Systems

Data-Acquisition Systems

Avionics

Robotics

Features

♦ Software-Programmable Input Range for Each

Channel

♦ Single-Ended Input Ranges

0 to +V

REF

/2, -V

REF

/2 to 0, 0 to +V

REF

, -V

REF

to 0, ±V

REF

/4, ±V

REF

/2, and ±V

REF

♦ Differential Input Ranges

±V

REF

/2, ±V

REF

, and ±2 x V

REF

♦ Eight Single-Ended or Four Differential Analog

Inputs (MAX1302)

♦ Four Single-Ended or Two Differential Analog

Inputs (MAX1303)

♦ ±6V Overvoltage Tolerant Inputs

♦ Internal or External Reference

♦ 115ksps Maximum Sample Rate

♦ Single +5V Power Supply

♦ 20-/24-Pin TSSOP Package

MAX1302/MAX1303

8-/4-Channel, ±V

REF

Multirange Inputs,

Serial 16-Bit ADCs

________________________________________________________________ Maxim Integrated Products 1

Pin Configurations

Ordering Information

AGND1

AGND2

DD2

AGND3CH2

CH1

CH0

DD1

TOP VIEW

REF

REFCAP

DDO

CH6

CH5

CH4

CH3

DGND

DGNDO

DOUT

SCLKSSTRB

DIN

CH7

TSSOP

MAX1302

19-3576; Rev 1; 12/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART

PIN-

PACKAGE

C H A N N EL S

PKG CODE

MAX1302AEUG*

24 TSSOP 8 U24-1

MAX1302BEUG*

24 TSSOP 8 U24-1

MAX1303AEUP* 20 TSSOP 4 U20-2

MAX1303BEUP 20 TSSOP 4 U20-2

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Pin Configurations continued at end of data sheet.

*Future product—contact factory for availability.

Note: All devices are specified over the -40°C to +85°C oper-

ating temperature range.

Summary of content (31 pages)

PAGE 1
9-3576; Rev 1; 12/06 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs The MAX1302/MAX1303 multirange, low-power, 16-bit, successive-approximation, analog-to-digital converters (ADCs) operate from a single +5V supply and achieve throughput rates up to 115ksps. A separate digital supply allows digital interfacing with 2.7V to 5.25V systems using the SPI™-/QSPI™-/MICROWIRE™-compatible serial interface. Partial power-down mode reduces the supply current to 1.3mA (typ).
PAGE 2
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs ABSOLUTE MAXIMUM RATINGS AVDD1 to AGND1 ....................................................-0.3V to +6V AVDD2 to AGND2 ....................................................-0.3V to +6V DVDD to DGND ........................................................-0.3V to +6V DVDDO to DGNDO ..................................................-0.3V to +6V DVDD to DVDDO ......................................................-0.
PAGE 3
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Preamplifier Supply Voltage AVDD2 4.75 5.
PAGE 6
ELECTRICAL CHARACTERISTICS (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 7
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs DIGITAL I/O SUPPLY CURRENT vs. DIGITAL I/O SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE 0.53 TA = +85°C TA = +85°C 0.20 PARTIAL POWER-DOWN MODE IAVDD1 (mA) IDVDDO (mA) 0.24 MAX1302/03 toc05 EXTERNAL CLOCK MODE 0.26 0.22 0.55 MAX1302/03 toc04 0.28 TA = +25°C 0.18 0.16 0.51 TA = +25°C 0.49 TA = -40°C TA = -40°C 0.14 0.47 0.12 0.10 0.45 4.75 4.85 4.95 5.05 5.15 4.75 4.85 4.95 5.05 5.
PAGE 8
Typical Operating Characteristics (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.) PREAMPLIFIER SUPPLY CURRENT vs. CONVERSION RATE ANALOG SUPPLY CURRENT vs. CONVERSION RATE MAX1302/03 toc09 EXTERNAL CLOCK MODE 2.5 25 MAX1302/03 toc08 3.
PAGE 9
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs EXTERNAL REFERENCE INPUT CURRENT vs. EXTERNAL REFERENCE INPUT VOLTAGE 0.14 0.04 0.02 0 -0.02 ±VREF/4 BIPOLAR 0.8 0.6 3.85 3.90 3.95 4.00 4.05 -0.4 -0.08 -0.8 ±VREF BIPOLAR -1.0 -40 -15 10 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) CHANNEL-TO-CHANNEL ISOLATION vs. INPUT FREQUENCY COMMON-MODE REJECTION RATIO vs. FREQUENCY INTEGRAL NONLINEARITY vs.
PAGE 10
Typical Operating Characteristics (continued) (AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±VREF), CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.) SNR, SINAD, ENOB vs. SAMPLE RATE -SFDR, THD vs.
PAGE 11
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs -20 -30 -40 25,000 20,000 15,000 10,000 -50 5000 -60 0 1 10 100 1000 10,000 32,769 32,770 32,771 32,772 32,773 32,774 FREQUENCY (kHz) CODE NOISE HISTOGRAM (CODE CENTER) REFERENCE VOLTAGE vs.
PAGE 12
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs Pin Description PIN MAX1302 MAX1303 12 NAME FUNCTION Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD1 to AGND1 with a 0.1µF capacitor.
PAGE 13
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs PIN MAX1300 MAX1301 NAME FUNCTION 21 18 AGND3 Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. 22 19 AVDD2 Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD2 to AGND2 with a 0.1µF capacitor. 23 20 AGND2 Analog Ground 2.
PAGE 14
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs Power Supplies Track-and-Hold Circuitry To maintain a low-noise environment, the MAX1302 and MAX1303 provide separate power supplies for each section of circuitry. Table 1 shows the four separate power supplies. Achieve optimal performance using separate AVDD1, AVDD2, DVDD, and DVDDO supplies. Alternatively, connect AV DD1 , AV DD2 , and DV DD together as close to the device as possible for a convenient power connection.
PAGE 15
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303 CS 32 31 30 BYTE 3 29 28 27 26 25 24 23 22 BYTE 2 21 20 19 18 17 16 15 14 13 BYTE 1 12 11 9 10 8 7 6 5 4 3 2 1 SCLK BYTE 4 SSTRB DIN S C2 C1 C0 0 0 0 0 fSAMPLE ≈ fSCLK / 32 SAMPLING INSTANT tACQ ANALOG INPUT TRACK AND HOLD* DOUT HOLD TRACK HIGH IMPEDANCE HOLD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 HIGH IMPEDANCE *TRACK AND HOLD TIMING IS CONTROLLED
PAGE 16
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs CS SSTRB 32 31 30 BYTE 3 29 28 27 26 25 24 23 0 22 BYTE 2 21 20 19 0 18 0 17 C0 16 C1 15 C2 14 S 13 DIN 12 BYTE 1 11 9 10 8 7 6 5 4 3 2 1 SCLK BYTE 4 0 DOUT HIGH IMPEDANCE B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 fSAMPLE ≈ fSCLK / 32 + fINTCLK / 17 SAMPLING INSTANT tACQ ANALOG INPUT TRACK AND HOLD* HOLD TRACK HOLD 100ns to 400ns 17 16 15 14 3 2
PAGE 17
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303 CS SSTRB 24 23 0 22 BYTE 2 21 0 20 0 19 C0 18 C1 17 C2 16 S 15 DIN 14 BYTE 1 13 12 11 9 10 8 7 6 5 4 3 2 1 SCLK BYTE 3 0 DOUT B15 HIGH IMPEDANCE B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 fSAMPLE ≈ fSCLK / 24 + fINTCLK / 28 SAMPLING INSTANT tACQ ANALOG INPUT TRACK AND HOLD* TRACK HOLD HOLD 100ns to 400ns 28 27 26 25 14 13 12 11 10 3 2 1 INTCLK** fINTCLK
PAGE 18
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs Table 3. Input Data Word Formats DATA BIT OPERATION D7 (START) D6 D5 D4 D3 D2 D1 D0 Conversion-Start Byte (Tables 4 and 5) 1 C2 C1 C0 0 0 0 0 Analog-Input Configuration Byte (Table 2) 1 C2 C1 C0 DIF/SGL R2 R1 R0 Mode-Control Byte (Table 7) 1 M2 M1 M0 1 0 0 0 CH6 CH7 Table 4.
PAGE 19
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs +3/4 VREF +3/2 VREF FSR = VREF +2 x VREF INPUT RANGE SELECTION BITS, R[2:0] EACH INPUT IS FAULT TOLERANT TO ±6V.
PAGE 20
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs Table 6.
PAGE 21
6 4 4 COMMON-MODE VOLTAGE (V) 6 2 0 -2 -4 2 0 -2 -4 VREF = 4.096V VREF = 4.096V -6 -6 -8 -6 -4 -2 0 2 4 6 8 -8 -6 -4 INPUT VOLTAGE (V) Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = VREF) 0 2 4 6 8 Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 2 x VREF) Output Data Format Output data is clocked out of DOUT in offset binary format on the falling edge of SCLK, MSB first (B15). For output binary codes, see the Transfer Function section and Figures 12, 13, and 14.
PAGE 22
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs FSR FSR FFFF FFFE FFFD 8001 8000 7FFF 8001 FSR BINARY OUTPUT CODE (LSB [hex]) FFFE FFFD FSR BINARY OUTPUT CODE (LSB [hex]) FFFF 8000 7FFF 0003 0003 0002 0002 1 LSB = FSR x VREF 65,536 x 4.096V 0001 1 LSB = 0001 FSR x VREF 65,536 x 4.096V 0000 0000 -32,768 -32,766 -1 0 +1 0 +32,765 +32,767 1 2 3 32,768 65,533 65,535 INPUT VOLTAGE (LSB [DECIMAL]) (AGND1) AGND1 (DIF/SGL = 0) 0V (DIF/SGL = 1) Figure 13.
PAGE 23
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs CS tCL tCH tCSH 1 SCLK 8 tCP tDS DIN START SEL2 SEL1 SEL0 1 8 tDH DIF/SGL R2 R1 R0 START M2 ANALOG INPUT CONFIGURATION BYTE tDV DOUT M1 M0 1 0 0 0 MODE CONTROL BYTE tTR HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing SSTRB tSSCS CS tCSS SCLK tDO DOUT HIGH IMPEDANCE MSB NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
PAGE 24
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs Table 8. Mode-Control Bits M[2:0] M2 M1 M0 0 0 0 External Clock (DEFAULT) MODE 0 0 1 External Acquisition 0 1 0 Internal Clock 0 1 1 Reserved 1 0 0 Reset 1 0 1 Reserved 1 1 0 Partial Power-Down 1 1 1 Full Power-Down External Acquisition Mode (Mode 1) The slowest maximum throughput rate is achieved with the external acquisition method.
PAGE 25
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs REF. When using the internal reference, bypass REFCAP with a 0.1µF or greater capacitor to AGND1 and bypass REF with a 1.0µF or greater capacitor to AGND1. • Partial power-down-mode control byte This prevents the MAX1302/MAX1303 from inadvertently exiting full power-down mode because of a CS glitch in a noisy digital environment.
PAGE 26
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs V+ 1.0µF IN 4.096V SAR ADC REF REF OUT 1.0µF MAX6341 AVDD1 1x REFCAP MAX1302 MAX1303 GND 5kΩ VRCTH 4.096V BANDGAP REFERENCE AGND1 Figure 18. External Reference Operation Bridge Application Layout, Grounding, and Bypassing The MAX1302/MAX1303 convert 1kHz signals more accurately than a similar sigma-delta converter that might be considered in bridge applications.
PAGE 27
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303 4–20mA INPUT CH0 µC 200Ω MAX1302 4–20mA INPUT CH8 200Ω Figure 19. 4–20mA Application LOW-OFFSET DIFFERENTIAL AMPLIFIER CH0 µP CH1 MAX1302 MAX1303 REF BRIDGE Figure 20. Bridge Application Differential Nonlinearity (DNL) Channel-to-Channel Isolation DNL is the difference between an actual step width and the ideal value of 1 LSB.
PAGE 28
MAX1302/MAX1303 8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs Unipolar Offset Error -FSR to 0V When a zero-scale analog input voltage is applied to the converter inputs, the digital output is all ones (0xFFFF). Ideally, the transition from 0xFFFF to 0xFFFE occurs at AGND1 - 0.5 LSB. Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded.
PAGE 29
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs  SINAD − 1.76  ENOB =     6.02 SCLK (MODE 0) 13 14 SCLK (MODE 1) 15 16 INTCLK (MODE 2) 10 11 MAX1302/MAX1303 Effective Number of Bits (ENOB) ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate.
PAGE 30
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303 Block Diagram SERIAL I/O CONTROL LOGIC AND REGISTERS CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND1 AVDD2 CLOCK ANALOG INPUT MUX AND MULTIRANGE CIRCUITRY PGA IN SAR ADC OUT DVDD FIFO DGND AVDD1 AGND3 REF AGND2 4.
PAGE 31
8-/4-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADCs TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 G 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.