Instruction Manual

MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS (Figures 1, 2, and 5)
(V
DD
= +2.7V to +3.6V, V
REF
= +2.5V, 0.1µF capacitor at REF, or V
DD
= +4.75V to +5.25V for MAX1286/MAX1288, V
REF
= +4.096V,
0.1µF capacitor at REF, f
SCLK
= 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289. T
A
= T
MIN
to T
MAX,
unless otherwise
noted. Typical values at T
A
= +25°C.)
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Pulse Width High t
CH
38 ns
SCLK Pulse Width Low t
CL
38 ns
SCLK Fall to DOUT Transition t
DOT
C
LOAD
= 30pF 60 ns
SCLK Rise to DOUT Disable t
DOD
C
LOAD
= 30pF
100
500 ns
CNVST Rise to DOUT Enable t
DOE
C
LOAD
= 30pF 80 ns
CNVST Fall to MSB Valid t
CONV
C
LOAD
= 30pF 3.7 µs
CNVST Pulse Width t
CSW
30 ns
Note 1: Unipolar mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled.
Note 4: The absolute input voltage range for the analog inputs is from GND to V
DD
.
• • •
• • •
• • •
CNVST
SCLK
DOUT
t
DOE
HIGH-Z
HIGH-Z
t
CSW
t
CL
t
CH
t
DOD
t
DOT
DOUT
6kΩ
6kΩ
C
L
GND
DOUT
C
L
GND
V
DD
a) HIGH -Z TO V
OH
, V
OL
TO V
OH
, AND V
OH
TO HIGH -Z
b) HIGH -Z TO V
OL
, V
OH
TO V
OL
, AND V
OL
TO HIGH -Z
Figure 1. Detailed Serial-Interface Timing Sequence
Figure 2. Load Circuits for Enable/Disable Times