User guide

MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 250MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential R
L
= 100Ω ±1%, C
L
= 5pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥25°C guar-
anteed by production test, <25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP MAX
UNITS
Clock Duty Cycle Set by clock management circuit
40 to 60
%
Aperture Delay t
AD
350 ps
Aperture Jitter t
AJ
0.2
ps
RMS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 2) 200 500
mV
P-P
Clock Input Common-Mode
Voltage Range
1.15
±0.25
V
Clock Differential Input
Resistance
R
CLK
11 ±
25%
kΩ
Clock Differential Input
Capacitance
C
CLK
5pF
DYNAMIC CHARACTERISTICS (at -0.5dBFS)
f
IN
= 10MHz, T
A
≥ +25°C
54.3 57.1
f
IN
= 100MHz, T
A
≥ +25°C54
56.8
f
IN
= 180MHz
56.3
Signal-to-Noise Ratio SNR
f
IN
= 500MHz
55.5
dB
f
IN
= 10MHz, T
A
≥ +25°C5457
f
IN
= 100MHz, T
A
≥ +25°C
53.5 56.5
f
IN
= 180MHz 56
Signal-to-Noise
and Distortion
SINAD
f
IN
= 500MHz 55
dB
f
IN
= 10MHz, T
A
≥ +25°C
62.6
75
f
IN
= 100MHz, T
A
≥ +25°C6271
f
IN
= 180MHz
68.3
Spurious-Free
Dynamic Range
SFDR
f
IN
= 500MHz
63.8
dBc
f
IN
= 10MHz -75
f
IN
= 100MHz -71
f
IN
= 180MHz
-68.3
Worst Harmonics
(HD2 or HD3)
f
IN
= 500MHz
-63.8
dBc
IMD
100
f
IN1
= 99MHz at -7dBFS,
f
IN2
= 101MHz at -7dBFS
-65
Two-Tone Intermodulation
Distortion
IMD
500
f
IN1
= 498.5MHz at -7dBFS,
f
IN2
= 502.5MHz at -7dBFS
-56
dBc
LVDS DIGITAL OUTPUTS (D0P/N–D9P/N, DCLKP/N)
Differential Output Voltage |V
OD
| 250 400 mV