User Manual

MAX11008
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
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Bypass the AV
DD
supply with a 0.1µF capacitor to
AGND, and place the capacitor as physically close as
possible to the AV
DD
input. Bypass the DV
DD
supply
with a 0.1µF capacitor to DGND, and place the capacitor
as physically close as possible to the DV
DD
input. If the
power supply is very noisy, connect a 10Ω resistor in
series with the supply input to improve power-supply fil-
tering.
DATA BITS BIT NAME RESET STATE FUNCTION
D[15:8] MSGL[7:0] 0000 0000
Message length bits. Specifies the length of the message to be read from
the EEPROM in words. The actual length read is MSGL + 1.
D[7:0] MSGA[7:0] 0000 0000
Message address bits. Specifies the starting address of the message to be
read from the EEPROM.
Table 23. Message Register
DATA BITS BIT NAME RESET STATE FUNCTION
D[15:12]
DATA[15:12]/
TAG[3:0]
0000
Message mode data bits/LUT streaming mode data bits/ADC channel tag
bits. See Table 24a.
D[11:0] DATA[11:0] 0000 0000 0000 Message data bits/ADC data bits.
Table 24. FIFO Read Register
DATA BITS BIT NAME RESET STATE FUNCTION
D[15:2] Unused X Unused bits.
D1 LDDACCH2 NA
Channel 2 load DAC bit. Set to 1 to transfer DAC2 input register contents to
DAC2 output register.
D0 LDDACCH1 NA
Channel 1 load DAC bit. Set to 1 to transfer DAC1 input register contents to
DAC1 output register.
Table 22. Load DAC Register
X = Don’t care.
NA = Not applicable.
AGND TRACE
AGND TRACE
DXP_ TRACE
DXN_ TRACE
10mils
10mils
10mils
10mils
Figure 23. Recommended DXP_ and DXN_ PCB Trace Layout