User Manual

MAX11008
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
6 _______________________________________________________________________________________
SPI TIMING CHARACTERISTICS (Notes 14, 15, Figure 1)
(DV
DD
= +2.7V to +5.25V, AV
DD
= +4.75V to +5.25V, V
DGND
= V
AGND
= 0, external V
REFADC
= +2.5V, external V
REFDAC
= +2.5V,
C
REF
= 0.1µF, T
A
= -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Clock Period t
CP
62.5 ns
SCLK High Time t
CH
25 ns
SCLK Low Time t
CL
25 ns
DIN to SCLK Rise Setup Time t
DS
15 ns
DIN to SCLK Rise Hold Time t
DH
0ns
SCLK Fall to DOUT Transition t
DO
C
L
= 30pF 20 ns
CS Fall to DOUT Enable t
DV
C
L
= 30pF 50 ns
CS Rise to DOUT Disable t
TR
C
L
= 30pF (Note 16) 50 ns
CS Rise or Fall to SCLK Rise t
CSS
12.5 ns
CS Pulse-Width High t
CSW
50 ns
Last SCLK Rise to CS Rise t
CSH
0ns
I
2
C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4)
(DV
DD
= +2.7V to +5.25V, AV
DD
= +4.75V to +5.25V, V
DGND
= V
AGND
= 0, external V
REFADC
= +2.5V, external V
REFDAC
= +2.5V,
C
REF
= 0.1µF, T
A
= -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency f
SCL
0 400 kHz
Bus Free Time Between a STOP
and START Condition
t
BUF
1.3 µs
Hold Time (Repeated) for START
Condition
t
HD:STA
After this period, the first clock pulse is
generated
0.6 µs
Setup Time for a Repeated
START Condition
t
SU:STA
0.6 µs
SCL Pulse-Width Low t
LOW
1.3 µs
SCL Pulse-Width High t
HIGH
0.6 µs
Data Setup Time t
SU:DAT
100 ns
Data Hold Time t
HD:DAT
(Note 17) 0.004 0.9 µs
SDA, SCL Rise Time t
R
Receiving (Note 18) 0 300 ns
SDA, SCL Fall Time t
F
Receiving (Note 18) 0 300 ns
SDA Fall Time t
F
Transmitting (Notes 18, 19)
20 + 0.1
x C
B
250 ns
Setup Time for STOP Condition t
SU:STO
0.6 µs
Capacitive Load for Each Bus
Line
C
B
(Note 20) 400 pF
Pulse Width of Spikes
Suppressed by the Input Filter
t
SP
(Note 21) 50 ns