User Manual
MAX11008
EEPROM
The MAX11008 features 4Kb of EEPROM capable of
storing up to 256 16-bit data words. The first 64 data
words of the EEPROM contain configuration data (see
Table 4) while the remaining 192 data words are pro-
grammable and used for storing temperature and APC
LUTs. The MAX11008 utilizes the LUT values to perform
gate voltage calculations (see the
V
GATE
_ Output
Equation
section). See the
First-In-First-Out (FIFO)
,
LUT
Streaming Mode
, and
Message Mode
sections for more
information on how to program and read from the
EEPROM. See the
Temperature/APC LUT Configuration
Registers
section for information on how to configure
the LUTs and how values are retrieved from the LUTs
for V
GATE_
calculations. See Table 5.
Nonvolatile Initialization Values
Upon power-on reset, the data contained within specif-
ic EEPROM locations is copied directly to correspond-
ing locations within the register address map
depending on the state of the magic number (see the
Magic Number
section).
• Locations 0x10–0x1F are directly copied to their cor-
responding locations within the register address
map.
• Locations 0x2C–0x33 are conditionally copied to
their corresponding locations within the register
address map. Set the MSB (labeled WCTRAM) to 1
for locations 0x2C–0x33 to be copied to the register
address map (see Table 4a).
By correctly configuring the initialization values stored
within the EEPROM, the MAX11008 can automatically
enter V
GATE_
compensation mode without the need for
a host processor. This autonomous operation is useful
in some application areas where a host controller is not
desired.
Changes made to the working registers during opera-
tion are volatile. To change a register’s nonvolatile ini-
tialization value, the corresponding EEPROM location
must be written by the LUT streaming protocol.
Magic Number
The address location 0x37 of the EEPROM is referred
to as the magic address. If the magic address is pro-
grammed with the magic number (0xAA55), the values
stored in address locations 0x10–0x1F and 0x2C–0x33
are loaded into the working registers (
see the Register
Address Map
section) during power-up initialization.
Address locations 0x10–0x1F are unconditionally
loaded into the working registers, whereas address
locations 0x2C–0x33 are only loaded if bit D15
(WCTRAM) of the address is set to 1. If magic address
location 0x37 is not programmed with the magic num-
ber (0xAA55), the EEPROM is determined to be unpro-
grammed; the power-up initialization load is then
bypassed and the working registers default to their
power-on reset value.
LUT Values
The values stored within the LUT section of the
EEPROM are 16-bit signed (two’s complement)
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
40 ______________________________________________________________________________________
HEX MNEMONIC TABLE BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
10 EE_TH1 7 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
11 EE_TL1 8 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
12 EE_IH1 9 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
13 EE_IL1 10 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
14 EE_TH2 7 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
15 EE_TL2 8 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
16 EE_IH2 9 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
17 EE_IL2 10 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
18 EE_HCFIG 11 T1AVGCTL T1LIMIT2 T1LIMIT1 T1LIMIT0 FIFOSTAT ADCMON PG2SET1 PG2SET0 PG1SET1 PG1SET1 CKSEL1 CKSEL0 ADCREF1 ADCREF0 DACREF1 DACREF0
19 EE_ALMSCF 12 X X X X A2AVG T2AVG A1AVG T1AVG TALARM2 TWIN2 IALARM2 IWIN2 TALARM1 TWIN1 IALARM1 IWIN1
1A EE_SCFIG 13 T2AVGCTL T2LIMIT2 T2LIMIT1 T1LIMIT0 LDAC2 TCOMP2 APCCOMP2 TSRC2 APCSRC21 APCSRC20 LDAC1 TCOMP1 APCCOMP1 TSRC1 APCSRC11 APCSRC10
1B EE_ALMHCF 14 X X X X X AVGMON INTEMP2 ALMCMP ALMHYST1 ALMHYST0 ALMCLMP21 ALMCLMP20 ALMCLMP11 ALMCLMP10 ALMPOL ALMOPN
1C EE_VSET1 15 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1D EE_HIST_AP 16a T1HIST3 T1HIST2 T1HIST1 T1HIST0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1D EE_HIST_AP 16b T1HIST3 T1HIST2 T1HIST1 T1HIST0 X X X X A1AVGCTL A1LIMIT2 A1LIMIT1 A1LIMIT0 A1HIST3 A1HIST2 A1HIST1 A1HIST0
1E EE_VSET2 15 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1F EE_HIST_AP 16a T1HIST3 T1HIST2 T1HIST1 T1HIST0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1F EE_HIST_AP 16b T2HIST3 T2HIST2 T2HIST2 T2HIST0 X X X X A2AVGCTL A2LIMIT2 A2LIMIT1 A2LIMIT0 A2HIST3 A2HIST2 A2HIST1 A2HIST0
2C EE_IDAC1 17 WCTRAM X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2D EE_IODAC1 18 WCTRAM X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2E EE_IDAC2 17 WCTRAM X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2F EE_IODAC2 18 WCTRAM X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
30 EE_PGACAL 19 WCTRAM X X X X X X X X X X X X TRACK DOCAL SELFTIME
31 EE_ADCCON 20 WCTRAM X X X X X X X CONCONV ADCIN2 CS2 EXTTEMP2 ADCIN1 CS1 EXTEMP1 INTEMP
32 EE_SSHUT 21 WCTRAM X X X X X X X X X X X FBGON OSCPD DAC2PD DAC1PD
33 EE_LDAC 22 WCTRAM X X X X X X X X X X X X X DAC_CH2 DAC_CH1
37 MAGIC NUMBER — 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1
3C EE_TLUT1 5 POFF5 POFF4 POFF3 POFF2 POFF1 POFF0 INT1 INT0 PSIZE1 PSIZE0 TSIZE2 TSIZE1 TSIZE0 SOT2 SOT1 SOT0
3D EE_ALUT1 5 POFF5 POFF4 POFF3 POFF2 POFF1 POFF0 INT1 INT0 PSIZE1 PSIZE0 TSIZE2 TSIZE1 TSIZE0 SOT2 SOT1 SOT0
3E EE_TLUT2 5 POFF5 POFF4 POFF3 POFF2 POFF1 POFF0 INT1 INT0 PSIZE1 PSIZE0 TSIZE2 TSIZE1 TSIZE0 SOT2 SOT1 SOT0
3F EE_ALUT2 5 POFF5 POFF4 POFF3 POFF2 POFF1 POFF0 INT1 INT0 PSIZE1 PSIZE0 TSIZE2 TSIZE1 TSIZE0 SOT2 SOT1 SOT0
Table 4a. EEPROM Address Bit Map