9-4371; Rev 0; 11/08 KIT ATION EVALU E L B A AVAIL Dual RF LDMOS Bias Controller with Nonvolatile Memory Features The MAX11008 controller biases RF LDMOS power devices found in cellular base stations and other wireless infrastructure equipment. Each controller includes a high-side current-sense amplifier with programmable gains of 2, 10, and 25 to monitor the LDMOS drain current over a range of 20mA to 5A.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory ABSOLUTE MAXIMUM RATINGS AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CS_+, CS_- to AGND .............................................-0.3V to +34V CS_+ to CS_If CS_+ > 6V .........................................................-0.
Dual RF LDMOS Bias Controller with Nonvolatile Memory (VCS_+ = +32V, AVDD = DVDD = +5V ±5%, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, CGATE_ = 0.1nF, VSENSE = VCS_+ - VCS_-, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LDMOS GATE DRIVER (Gain = 2) Output Gate-Drive Voltage Range IGATE_ = ±0.1mA 0.1 AVDD 0.1 IGATE_ = ±2mA 0.75 AVDD 0.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory ELECTRICAL CHARACTERISTICS (continued) (VCS_+ = +32V, AVDD = DVDD = +5V ±5%, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, CGATE_ = 0.1nF, VSENSE = VCS_+ - VCS_-, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MONITOR ADC CONVERSION RATE Power-Up Time (External Reference) tPUEXT 1.
Dual RF LDMOS Bias Controller with Nonvolatile Memory (VCS_+ = +32V, AVDD = DVDD = +5V ±5%, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, CGATE_ = 0.1nF, VSENSE = VCS_+ - VCS_-, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory SPI TIMING CHARACTERISTICS (Notes 14, 15, Figure 1) (DVDD = +2.7V to +5.25V, AVDD = +4.75V to +5.25V, VDGND = VAGND = 0, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Clock Period tCP 62.
Dual RF LDMOS Bias Controller with Nonvolatile Memory (DVDD = +2.7V to +5.25V, AVDD = +4.75V to +5.25V, VDGND = VAGND = 0, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER Serial Clock Frequency Setup Time (Repeated) START Condition Hold Time (Repeated) START Condition SCL Pulse-Width Low SCL Pulse-Width High SYMBOL CB = 100pF max CB = 400pF UNITS MIN MAX MIN MAX fSCL 0 3.4 0 1.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory MISCELLANEOUS TIMING CHARACTERISTICS (Note 15) (continued) (DVDD = +2.7V to +5.25V, AVDD = +4.75V to +5.25V, VDGND = VAGND = 0, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA = -40°C to +85°C, unless otherwise noted.
Dual RF LDMOS Bias Controller with Nonvolatile Memory ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE 3.0 IDVDD (mA) 2.09 2.08 0.2 2.5 2.0 MAX11008 toc03 AVDD = 5V WD OSC TURNED ON 0 PGAOUT_ ERROR (%) DVDD = 5V INT REF AND DACS TURNED ON MAX11008 toc02 3.5 MAX11008 toc01 2.10 -0.2 AFTER CALIBRATION -0.4 BEFORE CALIBRATION 2.07 -0.6 1.5 2.06 4.8 4.9 5.0 5.1 5.2 5.3 2.70 3.22 3.74 4.26 4.78 -40 5.30 50 80 110 CURRENT-SENSE AMPLIFIER OUTPUT ERROR vs.
Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, external VREFADC = 2.5V, external VREFDAC = 2.5V, VCS_- = VCS_+ = 32V, CREF = 0.1µF, TA = +25°C, unless otherwise noted.) CURRENT-SENSE TRANSIENT RESPONSE (G = 2) CURRENT-SENSE TRANSIENT RESPONSE (G = 25) CURRENT-SENSE TRANSIENT RESPONSE (G = 10) MAX11008 toc10 VSENSE1 1V/div 0V VSENSE1 200mV/div 0V VPGAOUT1 1V/div 0V VPGAOUT1 1V/div 0V 0V 1µs/div 1µs/div GATE VOLTAGE TOTAL UNADJUSTED ERROR vs.
Dual RF LDMOS Bias Controller with Nonvolatile Memory 0.75 0.50 0.25 0 -0.25 -0.25 -0.50 -0.75 -0.75 1024 2048 3072 4096 60 0 1024 2048 3072 4096 0.1 1 10 100 1000 OUTPUT CODE FREQUENCY (kHz) ADC SFDR vs. FREQUENCY DIGITAL SUPPLY CURRENT vs. SAMPLING RATE ADC INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 70 60 7 6 5 4 3 50 1 10 FREQUENCY (kHz) 100 1000 0.1 1 10 100 SAMPLING RATE (ksps) 1000 2.
Typical Operating Characteristics (continued) (AVDD = DVDD = 5V, external VREFADC = 2.5V, external VREFDAC = 2.5V, VCS_- = VCS_+ = 32V, CREF = 0.1µF, TA = +25°C, unless otherwise noted.) 2.50 VREFDAC 2.49 2.48 -25 0 25 50 75 100 1.0 0.5 1 4.875 5.000 5.125 5.250 -50 -25 0 25 50 75 100 AVDD (V) TEMPERATURE (°C) ADC GAIN ERROR vs. ANALOG SUPPLY VOLTAGE ADC GAIN EROR vs. TEMPERATURE RELATIVE TEMPERATURE ERROR vs. TEMPERATURE ADC GAIN ERROR (LSB) 2.0 1.5 1.0 0.5 2 1 0 -1 -2 5.
Dual RF LDMOS Bias Controller with Nonvolatile Memory PIN NAME 1, 31 DGND FUNCTION 2 OPSAFE1 3 A0/CS Address-Select Input 0/Chip-Select Input. In I2C mode, this is the address-select input 0. See Table 1. In SPI mode, this is the chip-select input. 4 CNVST Active-Low Conversion Start Input. Drive CNVST low to begin a conversion when in clock modes 01 and 11. 5 SPI/I2C Interface-Select Input. Connect to DGND for I2C interface. Connect to DVDD for SPI interface. 6 ALARM Digital Ground.
Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 Functional Diagram A2/N.C. A1/DOUT A0/CS DVDD AVDD PGAOUT1 MAX11008 SCL/SCLK SERIAL INTERFACE SDA/DIN SPI/I2C CS1+ PGA 1 CS1- FIFO AV = 2 12-BIT DAC1 GATE1 OPSAFE1 EEPROM REGISTER MAP AND DIGITAL CONTROL ALARM CS2+ BUSY PGA 2 CS2PGAOUT2 AV = 2 12-BIT DAC 2 GATE2 OPSAFE2 DXP1 REFDAC 2.
Dual RF LDMOS Bias Controller with Nonvolatile Memory DVDD AVDD 32V 0.1µF 0.1µF 4.7kΩ DVDD 4.7kΩ AVDD CS1+ 5V CF* RSENSE CS1- SCL/SCLK RF* SDA/DIN A0/CS CS2+ A1/DOUT CF* A2/N.C. RSENSE CS2- µC RF* OPSAFE1 MAX11008 GATE2 OPSAFE2 ALARM RF OUT BUSY CNVST RF IN LDMOS 1 SPI/I2C DXP2 REFADC EXTERNAL 2.5V REFERENCE DXN2 REFDAC 0.1µF 0.1µF GATE1 PGAOUT1 PGAOUT2 DXP1 RF OUT ADCIN1 DXN1 ADCIN2 DGND RF IN LDMOS 2 AGND *SDA RESISTOR VALUE VARIES WITH LOAD AND SCL FREQUENCY.
Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 Typical Application Circuits—SPI Interface AVDD DVDD 32V 0.1µF 0.1µF AVDD DVDD CS1+ 5V CF* SCL/SCLK RSENSE CS1RF* SDA/DIN A0/CS CS2+ A1/DOUT CF* RSENSE CS2µC RF* OPSAFE1 MAX11008 OPSAFE2 GATE2 ALARM BUSY RF OUT CNVST RF IN LDMOS 1 DVDD DXP2 SPI/I2C REFADC EXTERNAL 2.5V REFERENCE DXN2 REFDAC 0.1µF 0.
Dual RF LDMOS Bias Controller with Nonvolatile Memory The MAX11008 sets and controls the bias conditions for dual RF LDMOS power devices found in cellular base-station power amps. Each device includes two high-side current-sense amplifiers with programmable gains of 2, 10, and 25 to monitor the LDMOS transistor drain current over the 20mA to 5A range.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory The SPI bus cycles are 24 bits long. Data can be supplied as three 8-bit bytes or as a continuous 24-bit stream. CS must remain low throughout the 24-bit sequence. The first 8-bit byte is a command byte C[7:0]. The next 16 bits are data bits D[15:0]. Clock signal SCLK can idle low or high, but data is always clocked in on the rising edge of SCLK (CPOL = CPHA). SPI data transfers begin with the falling edge of CS.
Dual RF LDMOS Bias Controller with Nonvolatile Memory 1) Drive CS low to select the device. 2) Send the appropriate read command byte (see Table 6 for the register address map). The command byte is clocked in on the rising edges of SCLK. 3) Receive 16 bits of data. The first 4 bits of data are always high. Data is clocked out on the falling edges of SCLK. 4) Drive CS high. Figure 4 shows the 2-wire interface timing diagram.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory A master device communicates to the MAX11008 by transmitting the proper slave address followed by a command and/or data words. Each transmit sequence is framed by a START (S) or repeated START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse.
Dual RF LDMOS Bias Controller with Nonvolatile Memory Bus Timing At power-up, the bus timing is set for I2C fast-mode (F/S mode), which allows I2C clock rates up to 400kHz. The MAX11008 can also operate in high-speed mode (HS mode) to achieve I2C clock rates up to 3.4MHz. See Figure 4 for I2C bus timing. HS I2C Mode Select HS mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don’t care).
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 returns to F/S mode. Use a repeated START condition in place of a STOP condition to leave the bus active and the mode unchanged. Figure 9 summarizes the data bit transfer format for HS-mode communication. slave. The MSB of the register address byte is the read/write bit for the destination register address of the slave and must be set to 0 for a write cycle (see the Register Address Map section).
Dual RF LDMOS Bias Controller with Nonvolatile Memory contents of the register that was addressed in the previous command byte) to the master. Finally, the master issues a NACK followed by a STOP condition (P), ending the read cycle. Figure 11 shows a complete 5-byte read cycle. Default Read Cycle (3-Byte Read Cycle) The MAX11008 2-wire interface has a unique feature for read commands.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory 12-Bit ADC The MAX11008 12-bit ADC uses a SAR conversion technique and on-chip track-and-hold (T/H) circuitry to convert the PGA outputs (PGAOUT1 and PGAOUT2), temperature measurements, and single-ended auxiliary input voltages (ADCIN1 and ADCIN2) into 12-bit digital data when in ADC monitor mode (see the Hardware Configuration Register (HCFIG) (Read/Write) section).
Dual RF LDMOS Bias Controller with Nonvolatile Memory VREFADC 1111 1111 1111 FULL-SCALE TRANSITION ADC Conversion Scheduling The MAX11008 ADC multiplexer scans and converts the selected inputs in the order shown in Table 2 (see the ADC Conversion Register (ADCCON) (Write Only) section) when more than one channel is selected. The results are stored in the FIFO when in ADC monitoring mode.
complete the ADC powers down, BUSY is pulled low, and the results for all of the selected channels are available in the FIFO. The duration of the BUSY pulse is additive, depending on the channel conversion sequence selected. The BUSY pulse is set typically for 72µs by temperature conversions; 52µs by PGAOUT conversions, and 7µs by ADCIN conversions.
Dual RF LDMOS Bias Controller with Nonvolatile Memory Changing Clock Modes During ADC Conversions If a change is made to the clock mode in the configuration register while the ADC is already performing a conversion (or series of conversions), the following describes how the MAX11008 responds: • When CKSEL = 00 and is then changed to another value, the ADC completes the already triggered series of conversions and then goes idle. The BUSY output remains high until the conversions are completed.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Figure 16 shows the functional diagram of the MAX11008 DACs. Each DAC includes an input and output register. The input registers hold the result of the most recent write operation, and the output registers hold the current output code for the respective DAC. Data written to a DAC input register is transferred to its output register by writing to the Load DAC register (see Table 22).
Dual RF LDMOS Bias Controller with Nonvolatile Memory Temperature Sensors The MAX11008 measures the internal die temperature and two external LDMOS transistor temperatures through one internal and two external diode-connected transistors. The MAX11008 performs temperature measurements by changing the bias current of each diode from 4µA to 68µA to produce a temperature-dependent bias voltage difference. The internal ADC converts the voltage difference to a digital value.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory High-Side Current-Sense Amplifiers and PGAs The MAX11008 provides dual high-side current-sense and differential amplifier capability. The current-sense amplifiers provide a 5V to 32V input common-mode range. Both CS_+ and CS_- must be within the specified common-mode range for proper operation of each amplifier. The sense amplifiers measure the load current, ILOAD, through an external sense resistor, RSENSE, between the CS_+ and CS_- inputs.
Dual RF LDMOS Bias Controller with Nonvolatile Memory The BUSY output goes high during LUT streaming mode and returns low after all of the data is written to the EEPROM. FIFO data flow control in the LUT streaming mode can be implemented with the following methods: 1) Open Loop—Write data to the FIFO at a rate that does not exceed 1 word per 60µs to guarantee that the FIFO does not overflow.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory COUNT = 0 NO COUNT < MAX EXIT YES NO FLAG (FIFO_OVER_FLOW) = 0 FIFO FULL WAIT 60µs YES WRITE DATA TO FIFO COUNT = COUNT + 1 Figure 17.
Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 COUNT = 0 NO COUNT < MAX EXIT YES NO ALARM = 1 FIFO FULL WAIT 60µs YES WRITE DATA TO FIFO COUNT = COUNT + 1 Figure 18.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory high until the current scan is complete and the ADC sequence halts. In single-conversion mode (CKSEL1, CKSEL0 = 11), the BUSY signal remains high until the ADC has completed the current conversion (not the entire scan), the data has been moved into the FIFO, and the alarm limits for the channel have been checked (if alarm is enabled).
Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 (MEASUREMENT VALUE TEMPERATURE OR CURRENT) HIGH THRESHOLD BUILT-IN HYSTERESIS BUILT-IN HYSTERESIS LOW THRESHOLD TIME ALARM OUTPUT COMPARATOR MODE (ACTIVE LOW) INTERRUPT MODE (ACTIVE LOW) TIME ALARM FLAG REGISTER READ ALARM FLAG REGISTER READ ALARM FLAG REGISTER READ Figure 19.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory MEASUREMENT VALUE (TEMPERATURE OR CURRENT) HIGH THRESHOLD LOW THRESHOLD TIME ALARM OUTPUT COMPARATOR MODE (ACTIVE LOW) INTERRUPT MODE (ACTIVE LOW) ALARM FLAG REGISTER READ ALARM FLAG REGISTER READ TIME Figure 21.
Dual RF LDMOS Bias Controller with Nonvolatile Memory where: VGATE_ = actual gate voltage. VSET_ = factory-set DAC code at TCAL. LUTTEMP{Temp} = interpolated lookup value in the TEMP table for the sampled temperature. LUTAPC{APC} = interpolated lookup value in the APC table for the APC parameter. TCAL = temperature at which LUTTEMP{TCAL} returns 0; i.e., the calibration temperature. V SET_ is a 12-bit unsigned DAC code (0 to 4095).
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 4.
Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 Table 4. EEPROM Address Map (continued) WORD ADDRESS INTERFACE (CUSTOMER) COMMAND BIN DEC HEX MNEMONIC TABLE 0010 0000 32 20 — — 0010 0001 33 21 — — 0010 0010 34 22 — — 0010 0011 35 23 — — 0010 0100 36 24 — — 0010 0101 37 25 — — 0010 0110 38 26 — — 0010 0111 39 27 — — 0010 1000 40 28 — — 0010 1001 41 29 — — 0010 1010 42 2A — — 0010 1011 43 2B — — COMMENT Unused.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory EEPROM The MAX11008 features 4Kb of EEPROM capable of storing up to 256 16-bit data words. The first 64 data words of the EEPROM contain configuration data (see Table 4) while the remaining 192 data words are programmable and used for storing temperature and APC LUTs. The MAX11008 utilizes the LUT values to perform gate voltage calculations (see the V GATE _ Output Equation section).
Dual RF LDMOS Bias Controller with Nonvolatile Memory Temperature/APC LUT Configuration Registers The LUT Configuration register (see Table 5) specifies the location and the size of the temperature and automatic power control (APC) LUTs. The EEPROM can be configured to have a total of four LUTs (one temperature LUT for each temperature-sensor channel and one APC LUT for each DAC channel).
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory 4) The resulting LUT pointer value is bound-limited to ensure it fits within the corresponding LUT. Negative pointer values are limited to zero, and pointer values that extend beyond the range of the LUT are limited to the last entry. 5) The final LUT pointer value is calculated by shifting SOT to the left by 5 bits and then adding it to the current LUT pointer value.
Dual RF LDMOS Bias Controller with Nonvolatile Memory REGISTER ENTRY Temperature LUT1 APC LUT1 Temperature LUT2 APC LUT2 CONFIGURATION 1 (EXAMPLE) POFF = 010100 INT = 00 PSIZE = 01 TSIZE = 010 SOT = 100 0x5054 POFF = 000000 INT = 00 PSIZE = 00 TSIZE = 001 SOT = 010 0x000A POFF = 100000 INT = 00 PSIZE = 10 TSIZE = 010 SOT = 110 0x4096 POFF = 000000 INT = 00 PSIZE = 00 TSIZE = 001 SOT = 011 0x000B CONFIGURATION 2 (EXAMPLE) POFF = 010100 INT = 00 PSIZE = 01 TSIZE = 010 SOT = 100 0x5054 POFF = 000000 INT
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory ADC sample = 495 hex << x indicates a logical shift left by x number of bits. >> x indicates a logical shift right by x number of bits.
Dual RF LDMOS Bias Controller with Nonvolatile Memory Tables 7 to 27 describe each register in detail. Register Descriptions High Temperature Threshold Registers (TH1, TH2) (Read/Write) The High Temperature Threshold registers set the upper alarm thresholds for each temperature sensor channel (see Table 7).
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 6.
Dual RF LDMOS Bias Controller with Nonvolatile Memory Program PG_SET[1:0] to set the channel 1 and channel 2 current-sense amplifier gain (see Table 11c). Program CKSEL[1:0] to set the conversion and acquisition timing clock modes (see Table 11d). See the Internally Timed Acquisitions and Conversions section for detailed descriptions of each clock mode. Program ADCREF[1:0] to establish the source of the ADC reference (see Table 11e).
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 11. Hardware Configuration Register DATA BITS BIT NAME RESET STATE FUNCTION D15* T1AVGCTL 0 Channel 1 averaging-equation bit. This bit controls the averaging equation for channel 1 while the device is in tracking mode. See Table 11a. D[14:12]* T1LIMIT[2:0] 000 Channel 1 difference-limiter bits. Set T1LIMIT[2:0] to enable the difference limiter for channel 1 temperature averaging. See Table 11b.
Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 Table 11c. PGA1 and PGA2 Gain Setting Bits (PG_SET[1:0]) PG_SET1 PG_SET0 0 0 PGA GAIN 2 0 1 10 1 X 25 X = Don’t care. Table 11d. Clock Mode and CNVST Bit (CKSEL[1:0]) CKSEL1 CKSEL0 0 0 0 1 1 0 1 1 ADC CONVERSION TYPE Internally timed acquisitions and conversions start by writing to the ADC Conversion register and enabling one or more channels. See the ADC Conversion Register (ADCCON) (Write Only) section.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Set T_AVG to 1 to enable the temperature averaging and filtering function for channel 1 and channel 2. The TSRC_ field in the SCFG register controls the source of the sample. Set TALARM_ to 1 to enable and to 0 to disable the alarm function for channel 1 and channel 2 temperature measurements.
Dual RF LDMOS Bias Controller with Nonvolatile Memory VSET Registers (VSET1, VSET2) (Read/Write) The VSET registers set the nominal GATE_ output code without any temperature or APC compensation (see Table 15). This value is input into the VGATE_ calculation (see the VGATE_ Output Equation section).
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 12. Alarm Software Configuration Register DATA BITS BIT NAME RESET STATE D[15:12] Unused X Unused bits. 0 Channel 2 APC averaging and filtering bit. Set to 1 to enable the APC averaging and filtering function for channel 2. The source of the sample is controlled by the APCSRC2 field in the Software Configuration register. 0 Channel 2 temperature averaging and filtering bit.
Dual RF LDMOS Bias Controller with Nonvolatile Memory DATA BITS BIT NAME RESET STATE FUNCTION D15* T2AVGCTL 0 Channel 2 averaging-equation bit. This bit controls the averaging equation for channel 2 while the device is in tracking mode. See Table 13a. D[14:12]* T2LIMIT[2:0] 000 Channel 2 difference-limiter bits. Set T2LIMIT[2:0] to enable the difference limiter for channel 2 temperature averaging. See Table 13b. D11 LDAC2 0 Channel 2 LDAC control bit.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 13a. Channel 2 Averaging Equation (T2AVGCTL) D15 CHANNEL 2 AVERAGING EQUATION 0 Average = average + 1/16 difference. 1 Average = average + 1/4 difference. Table 13b. Channel 2 Difference Limiter Bits (T2LIMIT[2:0]) D14 D13 D12 0 0 0 No limiting is applied. CHANNEL 2 DIFFERENCE LIMITER 0 0 1 Difference is limited to 1 LSB (1/8 of a degree). 0 1 0 Difference is limited to 3 LSBs (3/8 of a degree).
Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 Table 13d.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 14. Alarm Hardware Configuration Register DATA BITS BIT NAME RESET STATE D[15:11] Unused XXXXX D10* AVGMON FUNCTION Unused bits. 0 ADC average monitor enable bit. Set AVGMON to 1 to average the ADC sample. The ADC average is written to the FIFO. The tracking average has a unique channel tag and is distinguishable from the raw sample. The average monitoring is automatically suspended when in LUT streaming and message modes.
Dual RF LDMOS Bias Controller with Nonvolatile Memory ALMCLMP1 ALMCLMP0 CLAMP MODE ALARM CLAMP SELECT 0 0 Alarm report If an alarm is triggered by a current or temperature conversion, the ALARM bit is set (1) in the alarm Flag register. No further action is taken. 0 1 Clamp gate The GATE_ output clamps to AGND immediately, independent of alarms. 0 Clamp gate on alarm with clear The GATE_ output is clamped to AGND in response to any alarm trip on the corresponding channel.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory FIFO (see the Message Mode section) so that the data words can be read out through the serial interface. In message mode the FIFO is eight deep, and does not overflow. In ADC/average monitoring mode, the 12-bit ADC conversion results of each selected channel are copied into the FIFO so that the conversion results can be read out through the serial interface (see the ADC Monitoring Mode section).
Dual RF LDMOS Bias Controller with Nonvolatile Memory TxHIST[3:0] FUNCTION MAX11008 Table 16c. Temperature Hysteresis Limit Register Bits Table 16e. APC Hysteresis Limit Register Bits AxHIST[3:0] FUNCTION 0000 1 LSB (1/8 of a degree). I.e., no hysteresis 0000 1 LSB. I.e.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Software Clear Register (SCLR) (Write Only) Write to the Software Clear register to clear the internal registers with a single write command (see Table 25). Bits D[15:7] are don’t-care bits. FULLRST and ARMRST operate in conjunction with each other to allow a full hardware reset of the device. If ARMRST has been set to 1 by a previous write command, setting FULLRST to 1 initiates a full reset of the MAX11008.
Dual RF LDMOS Bias Controller with Nonvolatile Memory When in ADC monitoring mode, FIFOOVER is set to 1 when a FIFO overflow occurs. FIFOOVER remains at 1, even if the FIFO is subsequently read and no longer full. FIFOOVER is reset by reading the Flag register. When in LUT streaming mode or message mode, the FIFO is not permitted to overflow and FIFOOVER then denotes when the FIFO is full. FIFOOVER is set to 1 when the FIFO is full and immediately returns to 0 once a data word is moved out of the FIFO.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory LOWI_ is set to 1 when the individual channel 1 and channel 2 current-sense measurements exceed the individual channel 1 and channel 2 low current threshold and returns to 0 after the Flag register is read. LOWI2 is replaced by LOWT2 when the INTEMP2 bit is set in the Alarm Hardware Configuration register.
Dual RF LDMOS Bias Controller with Nonvolatile Memory as physically close as possible to the DVDD input. If the power supply is very noisy, connect a 10Ω resistor in series with the supply input to improve power-supply filtering. Table 22. Load DAC Register DATA BITS BIT NAME RESET STATE D[15:2] Unused X FUNCTION Unused bits. D1 LDDACCH2 NA Channel 2 load DAC bit. Set to 1 to transfer DAC2 input register contents to DAC2 output register. D0 LDDACCH1 NA Channel 1 load DAC bit.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 24a. FIFO Read Channel Tags (TAG[3:0]) CHANNEL TAGS ADC DATA DESCRIPTION TAG3 TAG2 TAG1 TAG0 0 0 0 0 Internal temperature sensor measurement. ADCMON bit must be set. 0 0 0 1 Channel 1 external temperature measurement. ADCMON bit must be set. 0 0 1 0 Channel 1 drain current measurement. ADCMON bit must be set. 0 0 1 1 ADCIN1 input measurement. ADCMON bit must be set.
Dual RF LDMOS Bias Controller with Nonvolatile Memory DATA BITS BIT NAME RESET STATE D[15:12] Reserved X Reserved bits. D11 ALUBUSY 1 ALU busy bit. Set to 1 when the MAX11008 is performing internal calculations. Set to 0 after calculations are complete. D10 RESTART 0 Restart flag bit. Set to 1 after a full software reset is performed. Returns to 0 after the Flag register is read. Set to 0 after initial power-up. D9 FIFOEMP 0 FIFO empty flag bit. Set to 1 when FIFO is empty.
MAX11008 Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 27. LUT Streaming Register DATA BITS BIT NAME RESET STATE FUNCTION D[15:8] LUTSL[7:0] 0 LUT length bits. Specifies the number of data words to be written to the EEPROM. Up to 256 data words can be written. The actual length written is LUTSL + 1. D[7:0] LUTSA[7:0] 0 LUT address bits. Specifies the starting address of the data to be written to the EEPROM.
Dual RF LDMOS Bias Controller with Nonvolatile Memory Intermodulation Distortion (IMD) N.C. CS2- CS2+ CS1- N.C. CS1+ DVDD DGND 23 AGND N.C. 39 22 AGND PGAOUT1 40 21 AGND A2/N.C. 41 20 AVDD N.C. 42 19 N.C. SCL/SCLK 43 18 GATE1 SDA/DIN 44 17 GATE2 A1/DOUT 45 16 PGAOUT2 BUSY 46 15 ADCIN2 DVDD 47 14 ADCIN1 13 DXN2 MAX11008 EP* 6 7 8 9 10 11 12 DXP1 DXP2 5 DXN1 4 REFADC 3 REFDAC 2 OPSAFE2 1 ALARM 48 SPI/I2C + CNVST PROCESS: BiCMOS N.C.
