User guide

ISD5100 – SERIES
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7.4.3. ISD5100 Series Aanalog Structure (right half) Description
SUM1
SU M2
Σ
2 (S2M 1,S2 M0)
FI LTE R
MU X
SUM2 SUMMING
AMP
ARRAY
2
FI LTO
LOW PASS
FILTER
IN TERN AL
CLOCK
MULTILEVEL
STO RAGE
ARRAY
1
(FLS0)
1
(FLPD)
ARRAY
ANA IN AMP
XCLK
(FLD1,FL D0)
15141312111098 76 54 32 10
VLS1
VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FL D1 FLD0 FLP D AGPD
CFG1
FLS0 SOURCE
0 SUM1
1 ARRAY
FLPD CONDITION
0 Power Up
1 Power Down
S2M1 S2M0 SOURCE
0 0 BOTH
0 1 ANA IN ONLY
1 0 FILTO ONLY
1 1 Power Down
FLD1 FLD0 SAMPLE
RATE
FILTER
BANDWIDTH
0 0 8 KHz 3.6 KHz
0 1 6.4 KHz 2.9 KHz
1 0 5.3 KHz 2.4 KHz
1 1 4.0 KHz 1.8 KHz
FILTER
MUX
FILTO