User guide

ISD5100 – SERIES

Publication Release Date: October, 2003

- 29 - Revision 0.2

7.4.2. ISD5100 Series Analog Structure (left half) Description

IN PUT

AGC AMP

SU M 1

2 (S1M1,S1M0)

SO UR CE

MU X

SUM1 SUMMING

AMP

AUX IN AMP

FI LTO

SU M1

MU X

AN A IN A MP

AR RA Y

2 (S1S1,S1S0)

(INS0)

1 5 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 1 0

AIG1

AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD

CFG0

1 5 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 1 0

VLS1 VL S0 V OL2 VOL1 V OL 0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD

CFG1

INP

INSO Source

0 AGC AMP

1 AUX IN AMP

S1M1 S1M0 SOURCE

0 0 BOTH

0 1 SUM1 MUX ONLY

1 0 INP Only

1 1 Power Down

S1S1 S1S0 SOURCE

0 0 ANA IN

0 1 ARRAY

1 0 FILTO

1 1 N/C