HT49R70A-1 8-Bit LCD Type OTP MCU Features · Operating voltage: 3.0V~5.
HT49R70A-1 Block Diagram In te rru p t C ir c u it U P ro g ra m C o u n te r M T M R 1 C T M R 1 P F D 1 IN T C U X fS In s tr u c tio n R e g is te r Y S /4 Y S R T C O P B 2 /T M P B 3 /T M T M R 0 O fS Y S T im e B fT 1 D X P F D 0 S T A C K P ro g ra m E P R O M fS fS M T M R 0 C T M R 0 Y S u t R 0 R 1 V a s e O u t /4 R T C M M P U X D A T A M e m o ry M W D T T im e B a s e M U X In s tr u c tio n D e c o d e r U R T C X O S C O S C 3 O S C 4 W D T O S C P C P C 0 ~
HT49R70A-1 Pin Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G O S C O S C V D O S C O S C R E P A 0 /B P A 1 /B P A P A 3 /P F P A D D S Z Z 4 2 0 4 3 2 1 1 2 3 4 5 6 7 8 P A N N N N N P A P A P B P B P B 2 P B 3 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 1 8 0 5 C 2 7 9 C 3 7 8 C 4 7 7 C 5 7 6 C 6 7 5 7 7 4 8 7 3 T 0 T 1 9 7 2 1 0 7 1 R 0 1 1 7 0 R 1 B 4 B 5 B 6 B 7 C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 N C N C N C N
HT49R70A-1 Pin Description Pin Name Options Description Wake-up Pull-high or None CMOS or NMOS PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. Each bit on port can be configured as a wake-up input by options. PA0~PA3 can be configured as a CMOS output or NMOS input/output with or without pull-high resistor by options. PA4~PA7 are always pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by options.
HT49R70A-1 D.C. Characteristics Symbol VDD Parameter Operating Voltage IDD1 Operating Current (Crystal OSC) IDD2 Operating Current (RC OSC) IDD3 Operating Current (fSYS=32768Hz) Ta=25°C Test Conditions VDD Conditions ¾ ¾ 3V 5V 3V 5V 3V 5V No load, fSYS=4MHz No load, fSYS=4MHz No load 3V No load, system HALT 5V LCD off at HALT Min. Typ. Max. Unit 3.0 ¾ 5.5 V ¾ 2.0 3.0 mA ¾ 5.0 8.0 mA ¾ 1.8 2.7 mA ¾ 4.6 7.5 mA ¾ 1.
HT49R70A-1 A.C. Characteristics Symbol Test Conditions Min. Typ. Max.
HT49R70A-1 Functional Description Execution flow After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
HT49R70A-1 · Location 008H When a control transfer takes place, an additional dummy cycle is required. Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H. Program memory - EPROM The program memory (EPROM) is used to store the program instructions which are to be executed.
HT49R70A-1 Stack register - STACK The stack register is a special part of the memory used to save the contents of the PC. The stack is organized into 8 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the PC is pushed onto the stack.
HT49R70A-1 Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack.
HT49R70A-1 INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further interrupts. gram which corrupts the desired control sequence, the contents should be saved in advance.
HT49R70A-1 Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 40kW to 680kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations.
HT49R70A-1 S y s te m C lo c k /4 R T C O S C 3 2 7 6 8 H z R O M C o d e O p tio n fS D iv id e r D iv id e r C K W D T 1 2 k H z O S C T C K R T R T im e - o u t R e s e t fS /2 1 6 W D T C le a r Watchdog Timer The WDT time-out period is fixed as fS/216. equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out.
HT49R70A-1 Real time clock - RTC The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a ²warm reset². After examining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared by system power-up or by executing the ²CLR WDT² instruction, and is set by executing the ²HALT² instruction.
HT49R70A-1 The functional unit chip reset status is shown below. The WDT time-out during HALT differs from other chip reset conditions, for it can perform a ²warm reset² that resets only the PC and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition² once the reset conditions are met. Examining the PD and TO flags, the program can distinguish between different ²chip resets².
HT49R70A-1 The register states are summarized below: Register Reset (Power On) WDT Time-out RES Reset (Norma Operation) (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* TMR xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR0C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- TMR1H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- 0000H 0000H 0000H 0
HT49R70A-1 S y s te m S y s te m R O M C o d e O p tio n C lo c k C lo c k /4 M f IN U T X D a ta B u s R T C O u t T N 1 T N 0 T N 2 T M R 0 T im e r /E v e n t C o u n te r 0 P r e lo a d R e g is te r R e lo a d T E T N 1 T N 0 T O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l O v e r flo w to In te rru p t T im e r /E v e n t C c o u n te r 0 T Q P F D 0 P A 3 D a ta C T R L Timer/Event Counter 0 Label (TMR0C) Bits ¾ 0~2 Function Unused bit, read as ²0² TE 3 Define
HT49R70A-1 S y s te m C lo c k R O M C o d e O p tio n T M R 0 O V M fS Y S f IN U T X T im e B a s e O u t D a ta B u s /4 T N 1 T N 0 T N 2 T M R 1 1 6 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r T E T N 1 T N 0 T O N O v e r flo w to In te rru p t 1 6 - b it T im e r /E v e n t C o u n te r (T M R 1 H /T M R 1 L ) P u ls e W id th M e a s u re m e n t M o d e C o n tro l T Q P F D 1 P A 3 D a ta C T R L Timer/Event Counter 1 Label (TMR1C) Bits ¾
HT49R70A-1 Input/output ports PA or PC. Since the read-modify-write will read the entire port state (pads state) first, execute the specified instruction and then write the result to the port data register. When the read operation is executed, a fault pad state (caused by the load effect or floating state) may be read. Errors will then occur. There are two 8-bit bidirectional input/output ports, PA and PC and one 8-bit input port PB.
HT49R70A-1 V V D a ta B u s W r ite D C /N O (P P Q C K D D D D W e a k P u ll- u p M O S p tio n A 0 ~ P A 3 , C ) O p tio n (P A 0 ~ P A 3 , P C ) V P A 0 ~ P A 7 P C 0 ~ P C 7 Q S D D W e a k P u ll- u p C h ip R e s e t D a ta b u s P B 0 ~ P B 7 R e a d I/O R e S W a (P A a d y s k e o I/O te m -u p n ly ) O p tio n Input/output ports Input ports memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1.
HT49R70A-1 pacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage can be 1/2bias or 1/3bias by option. If 1/2bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3bias is selected, two capacitors are needed for V1 and V2 pins. Refer to application diagram. LCD driver output The output number of the HT49R70A-1 LCD driver can be 41´2 or 41´3 or 40´4 by option (i.e., 1/2duty, 1/3duty or 1/4duty). The bias type LCD driver can be ²R² type or ²C² type.
HT49R70A-1 V A V B V C C O M 0 V S S V A V B V C C O M 1 V S S V A V B V C C O M 2 V S S V A V B C O M 3 V C V S S V A V B V C L C D s e g m e n ts O N C O M 2 s id e lig h te d V S S N o te : 1 /4 d u ty , 1 /3 b ia s , C ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D 1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D LCD driver output Rev. 1.
HT49R70A-1 Low voltage reset/detector functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the MCU. These two functions can be enabled/disabled by ROM code options. Once the LVD ROM code options is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled. The LVR has the same effect or function with the external RES signal which performs chip reset.
HT49R70A-1 Options Pull-high selection. This option is to decide whether the pull-high resistance is visible or not on the PA0~PA3 and PC. (PB and PA4~PA7 are always pull-high) PA0~PA3 and PC0~PC7 CMOS or NMOS selection. The structure of PA0~PA3 and PC0~PC7 can be selected as CMOS or NMOS individually. When the CMOS is selected, the related pins only can be used for output operations. When the NMOS is selected, the related pins can be used for input or output operations.
HT49R70A-1 Application Circuits R C o s c illa to r a p p lic a tio n C r y s ta l o s c illa to r a p p lic a tio n O S C 1 V O S C 1 S E G 0 ~ 3 9 C O M 0 ~ 3 D D L C D P A N E L S E G 0 ~ 3 9 C O M 0 ~ 3 L C D P A N E L O S C 2 V L C D fS Y S /4 O S C 2 V L C D P o w e r S u p p ly V V L C D D D L C D P o w e r S u p p ly D D C 1 C 1 0 .1 m F R E S C 2 0 .1 m F C 2 R E S H T 4 9 R 7 0 A -1 H T 4 9 R 7 0 A -1 V 1 0 .1 m F V 1 0 .1 m F O S C 3 V 2 O S C 3 V 2 0 .1 m F 0 .
HT49R70A-1 Instruction Set Summary Mnemonic Description Flag Affected Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to register with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory
HT49R70A-1 Mnemonic Description Flag Affected Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].
HT49R70A-1 Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
HT49R70A-1 AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ AND A,x Logical AND immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_AND operation.
HT49R70A-1 CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT and the WDT Prescaler are cleared (re-counting from 0). The power down bit (PD) and time-out bit (TO) are cleared.
HT49R70A-1 CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged.
HT49R70A-1 HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared.
HT49R70A-1 MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. Operation ACC ¬ x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory Description The contents of the accumulator are copied to the specified data memory (one of the data memories).
HT49R70A-1 RET Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Operation PC ¬ Stack Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
HT49R70A-1 RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].
HT49R70A-1 RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].
HT49R70A-1 SET [m] Set data memory Description Each bit of the specified data memory is set to 1. Operation [m] ¬ FFH Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SIZ [m] Skip if increment data memory is 0 Description The contents of the specified data memory are incremented by 1.
HT49R70A-1 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SUBM A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
HT49R70A-1 SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
HT49R70A-1 XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation.
HT49R70A-1 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd.
