Instruction Manual

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REV: 111003

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

GENERAL DESCRIPTION

The DS89C430, DS89C440, and DS89C450 offer the

highest performance available in 8051-compatible

microcontrollers. They feature newly designed

processor cores that execute instructions up to 12

times faster than the original 8051 at the same

crystal speed. Typical applications will experience a

speed improvement up to 10x. At 1 million

instructions per second (MIPS) per megahertz, the

microcontrollers achieve 33 MIPS performance from

a maximum 33MHz clock rate.

The Ultra-High-Speed Flash Microcontroller User’s Guide should

be used in conjunction with this data sheet. Download it at

www.maxim-ic.com/microcontrollers

APPLICATIONS

Data Logging Vending

Automotive Test Equipment Motor Control

Magstripe Reader/Scanner Consumer Electronics

Gaming Equipment Telephones

HVAC Programmable Logic

Controllers

Uninterruptible Power

Supplies

Building Security and

Door Access Control

Building Energy Control and

Management

Industrial Control and

Automation

White Goods (Washers,

Microwaves, etc.)

ORDERING INFORMATION

PART

FLASH

MEMORY SIZE

PIN-PACKAGE

DS89C430-MNL

16kB x 8 40 PDIP

DS89C430-QNL 16kB x 8 44 PLCC

DS89C430-ENL 16kB x 8 44 TQFP

DS89C440-MNL

32kB x 8 40 PDIP

DS89C440-QNL 32kB x 8 44 PLCC

DS89C440-ENL 32kB x 8 44 TQFP

DS89C450-MNL

64kB x 8 40 PDIP

DS89C450-QNL 64kB x 8 44 PLCC

DS89C450-ENL 64kB x 8 44 TQFP

Complete Selector Guide appears at end of data sheet.

Pin Configurations appear at end of data sheet.

FEATURES

§ High-Speed 8051 Architecture

One Clock-Per-Machine Cycle

DC to 33MHz Operation

Single Cycle Instruction in 30ns

Optional Variable Length MOVX to Access

Fast/Slow Peripherals

Dual Data Pointers with Automatic

Increment/Decrement and Toggle Select

Supports Four Paged Memory-Access Modes

§ On-Chip Memory

16kB/32kB/64kB Flash Memory

In-Application Programmable

In-System Programmable Through Serial Port

1kB SRAM for MOVX

§ 80C52 Compatible

8051 Pin and Instruction Set Compatible

Four Bidirectional, 8-Bit I/O Ports

Three 16-Bit Timer Counters

256 Bytes Scratchpad RAM

§ Power-Management Mode

Programmable Clock Divider

Automatic Hardware and Software Exit

§ ROMSIZE Feature

Selects Internal Program Memory Size from

0 to 64kB

Allows Access to Entire External Memory Map

Dynamically Adjustable by Software

§ Peripheral Features

Two Full-Duplex Serial Ports

Programmable Watchdog Timer

13 Interrupt Sources (Six External)

Five Levels of Interrupt Priority

Power-Fail Reset

Early Warning Power-Fail Interrupt

Electromagnetic Interference (EMI) Reduction

DS89C430/DS89C440/DS89C450

Ultra-High-Speed Flash Microcontrollers

www.maxim-ic.com

Summary of content (48 pages)

PAGE 1
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS89C430, DS89C440, and DS89C450 offer the highest performance available in 8051-compatible microcontrollers. They feature newly designed processor cores that execute instructions up to 12 times faster than the original 8051 at the same crystal speed. Typical applications will experience a speed improvement up to 10x.
PAGE 2
DS89C430/DS89C44/DS89C450 Ultra-High-Speed Flash Microcontrollers ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Voltage Range on VCC Relative to Ground Ambient Temperature Range (under bias) Storage Temperature Range Soldering Temperature -0.3V to (VCC + 0.5V) -0.3V to +6.0V -40°C to +85°C -55°C to +125°C See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 3
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Note 1: Note 2: Note 3: Specifications to -40°C are guaranteed by design and not production tested. All voltages are referenced to ground. The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that VRST (min) is specified below that point.
PAGE 4
DS89C430/DS89C440/DS89C450 AC CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.) PARAMETER SYMBOL 1-CYCLE PAGE MODE 1 2-CYCLE PAGE MODE 1 4-CYCLE PAGE MODE 1 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 0 33 0 33 0 33 0 33 0 33 System Clock External Oscillator (Note 15) 1/tCLCL System Clock External Crystal (Note 15) 1/tCLCL 1 ALE Pulse Width (Note 16) tLHLL 0.
PAGE 5
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers AC CHARACTERISTICS (continued) (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.
PAGE 6
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers AC CHARACTERISTICS (continued) (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.) PARAMETER SYMBOL Port 0 Address to Valid Data In (Note 16) tAVDV0 Port 2 Address to Valid Data In (Note 16) tAVDV2 ALE Low to RD or WR Low (Note 16) Port 0 Address Valid to RD or WR Low (Note 16) Port 2 Address Valid to RD or WR Low (Note 16) tLLRL (tLLWL) 1-CYCLE PAGE MODE 1 2-CYCLE PAGE MODE 1 MIN MIN MAX 0.
PAGE 7
DS89C430/DS89C440/DS89C450 Note 15: The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/ maximum external clock speed. The term “1/tCLCL” used in the AC Characteristics variable timing table is determined from the following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot exceed the rated speed of the device.
PAGE 8
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 2. Page Mode 1 Timing XTAL1 tCLCL tLHLL ALE tAVLL2 tPLPH tLLAX tLLAX3 PSEN tWHLH tLLAX2 tLLWL RD tRLRH WR tPXIX tRHDX tAVIV2 Port 0 MOVX MOVX tWLWH tAVWL2 tPLIV tRLDV OPCODE tWHQX tQVWX DATA DATA OPCODE tAVDV2 Port 2 LSB LSB LSB MSB LSB MSB LSB MSB LSB MSB Figure 3.
PAGE 9
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers EXTERNAL CLOCK CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) PARAMETER SYMBOL MIN MAX UNITS Clock High Time tCHCX 10 ns Clock Low Time tCLCX 10 ns Clock Rise Time tCLCH 5 ns Clock Fall Time tCHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.
PAGE 10
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 4.
PAGE 11
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers POWER-CYCLE TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) PARAMETER SYMBOL MIN TYP MAX UNITS Crystal Startup Time (Note 18) tCSU 8 ms Power-On Reset Delay (Note 19) tPOR 65,536 tCLCL Note 18: Startup time for a crystal varies with load capacitance and manufacturer. The time shown is for an 11.0592MHz crystal manufactured by Fox Electronics.
PAGE 12
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers PIN DESCRIPTION PIN NAME FUNCTION PDIP PLCC TQFP 40 12, 44 6, 38 VCC 20 1, 22, 23, 34 16, 17, 28, 39 GND Logic Ground 9 10 4 RST External Reset. The RST input pin is bidirectional and contains a Schmitt Trigger to recognize external active-high reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wire-ORed external reset sources.
PAGE 13
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers PIN DESCRIPTION (continued) PIN NAME PDIP PLCC TQFP 1 2 40 P1.0 2 3 41 P1.1 3 4 42 P1.2 4 5 43 P1.3 5 6 44 P1.4 6 7 1 P1.5 7 8 2 P1.6 8 9 3 P1.7 21 24 18 P2.0 (A8) 22 25 19 P2.1 (A9) 23 26 20 P2.2(A10) 24 27 21 P2.3(A11) 25 28 22 P2.4(A12) 26 29 23 P2.5(A13) 27 30 24 P2.6(A14) 28 31 25 P2.7(A15) 10 11 5 P3.0 11 13 7 P3.1 12 14 8 P3.2 13 15 9 P3.
PAGE 14
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 5.
PAGE 15
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Terminology The term DS89C430 is used in the remainder of the document to refer to the DS89C430, DS89C440, and DS89C450, unless otherwise specified. Compatibility The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the DS87C520, but it offers much higher performance. In most cases, the DS89C430 can drop into an existing socket for the 8xC51 family, immediately improving the operation.
PAGE 16
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers All standard SFR locations from the 8051 are duplicated in the DS89C430, and several SFRs have been added for the unique features of the DS89C430. Most of these features are controlled by bits in SFRs located in unused locations in the 8051 SFR map, allowing for increased functionality while maintaining complete instruction set compatibility. Table 1 shows the SFRs and their locations.
PAGE 17
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 1. SFR Register Map (continued) REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TH1 8Dh CKCON 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0 P1 90h P1.7/INT5 P1.6/INT4 P1.5/INT3 P1.4/INT2 P1.3/TXD1 P1.2/RXD1 P1.1/T2EX P1.
PAGE 18
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 2.
PAGE 19
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 2.
PAGE 20
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 6.
PAGE 21
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Program Memory Access On-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB) on the DS89C430, through 7FFFh (32kB) on the DS89C440, and through FFFFh (64kB) on the DS89C450. Exceeding the maximum address of on-chip program memory causes the device to access off-chip memory. The maximum on-chip decoded address is selectable by software using the ROMSIZE feature.
PAGE 22
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers fetch that takes four clocks. Page mode 1 is the only external addressing mode where the CPU does not require stalls for external memory access, but page misses result in reduced external access performance. On-Chip Program Memory The processor can fetch the entire on-chip program memory range automatically. By default, the reset routines and all interrupt vectors are located in the lower 128 bytes of the on-chip program memory.
PAGE 23
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Note: The read/write accessibility of the flash memory during in-application programming is not affected by the state of the lock bits. However, the lock bits do affect the read/write accessibility in ROM loader and parallel programming modes. In-Application Programming by User Software The DS89C430 supports in-application programming of on-chip flash memory by user software.
PAGE 24
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 4. In-Application Programming Commands FC3:FC0 COMMAND OPERATION 0000 Read Mode Default state. All flash blocks are in read mode. Note: The upper bank of flash memory is inaccessible for execution unless the FC3:0 bits are in the read mode (0000b) state. 0001 Verify Option Control Register Read data from the option control register. Data is available in the FDATA at the end of the following machine cycle. FDATA.
PAGE 25
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers ROM Loader The full on-chip flash program memory space, security flash block, and external SRAM can be programmed insystem from an external source through serial port 0 under the control of a built-in ROM loader. The ROM loader also has an auto-baud feature that determines which baud-rate frequencies are being used for communication and sets the baud-rate generator for that speed.
PAGE 26
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 5. Parallel Programming Instruction Set P2.5:0, P1.7:0 P0.7:0 PROG Don’t care Don’t care PL 1 H L L L Mass erase the program memory and the security block. The contents of every memory location is returned to FFh.
PAGE 27
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers DPTR instruction decrements the DPTR1 contents by 1. With this feature, the user can configure the data pointers to operate in four ways for the INC DPTR instruction: ID1 0 0 1 1 ID0 0 1 0 1 SEL = 0 INC DPTR DEC DPTR INC DPTR DEC DPTR SEL = 1 INC DPTR1 INC DPTR1 DEC DPTR1 DEC DPTR1 SEL (DPS.0) bit always selects the active data pointer.
PAGE 28
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 7. External Program Memory Access (Nonpage Mode, CD1:CD0 = 10) Internal Memory Cycles External Memory Cycle C1 C2 C3 C4 External Memory Cycle C1 C2 C3 C4 XTAL1 ALE PSEN LSB Add Data LSB Add Data Port 0 MSB Add Port 2 MSB Add External Data Memory Interface in Nonpage Mode Operation Just like the program memory cycle, the external data memory cycle is four times slower than the internal data memory cycle in nonpage mode.
PAGE 29
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers The following diagrams illustrate the timing relationship for external data memory access in full speed (stretch value = 0), in the default stretch setting (stretch value = 1), and slow data memory accessing (stretch value = 4), when the system clock is in divide-by-1 mode (CD1:CD0 = 10b). Figure 8.
PAGE 30
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Page Mode, External Memory Cycle Page mode retains the basic circuitry requirement for an original 8051 external memory interface, but alters the configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles. Additionally, the functions of ALE and PSEN are altered to support this mode of operation. Setting the PAGEE (ACON.7) bit to logic 1 enables page mode.
PAGE 31
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 10.
PAGE 32
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b: · · · PSEN is asserted for both a page hit and a page miss for a full clock cycle. The execution of external MOVX instruction causes a page miss. A page miss occurs when fetching the next external instruction following the execution of an external MOVX instruction. Figure 10 shows the external memory cycle for this bus structure.
PAGE 33
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 8. Page Mode 1, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 00) MD2:MD0 STRETCH CYCLES RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X/2X, CD1, CD0 = 100 4X/2X, CD1, CD0 = 000 4X/2X, CD1, CD0 = X10 4X/2X, CD1, CD0 = X11 000 0 0.25 0.5 1 1024 001 1 0.75 1.5 3 3072 010 2 1.75 3.5 7 7168 011 3 2.75 5.5 11 11,264 100 7 3.75 7.5 15 15,360 101 8 4.75 9.5 19 19,456 110 9 5.75 11.
PAGE 34
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Table 11. Page Mode 2, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 11) MD2:MD0 STRETCH CYCLES 000 RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X/2X, CD1, CD0 = 100 4X/2X, CD1, CD0 = 000 4X/2X, CD1, CD0 = X10 4X/2X, CD1, CD0 = X11 0 0.
PAGE 35
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 12.
PAGE 36
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 13.
PAGE 37
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Interrupt Priority There are five levels of interrupt priority: Level 4 to 0. The highest interrupt priority is level 4, which is reserved for the power-fail interrupt. All other interrupts have individual priority bits in the interrupt priority registers to allow each interrupt to be assigned a priority level from 3 to 0. The power-fail interrupt always has the highest priority if it is enabled.
PAGE 38
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Timer/Counters The DS89C430 incorporates three 16-bit timers. All three timers can be used as either counters of external events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. Table 13 summarizes the timer functions. Timers 0 and 1 both have three modes of operations. They can each be used as a 13-bit timer/counter, a 16-bit timer/counter, or an 8-bit timer/counter with autoreload.
PAGE 39
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers during the three machine cycles following the writing of the 55h. Writing to a timed-access-protected bit outside of these three machine cycles has no effect on the bit. The timed-access process is address, data, and time dependent. A processor running out of control and not executing system software statistically is not able to perform this timed sequence of steps, and as such, does not accidentally alter the protected bits.
PAGE 40
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Figure 14. System Clock Sources 4X/2X CTM CLOCK MULTIPLIER CRYSTAL OSCILLATOR MUX SYSTEM CLOCK DIVIDE 1024 RING OSCILLATOR RING ENABLE CD0 SELECTOR CD1 Bandgap-Monitored Interrupt and Reset Generation The power monitor in the DS89C430 monitors the VCC pin in relation to the on-chip bandgap voltage reference.
PAGE 41
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Watchdog Timer The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When the clock 17 divider is set to 10b, the interrupt timeout has a default divide ratio of 2 of the crystal oscillator clock, with the watchdog reset set to time out 512 system clock cycles later. This results in a 33MHz crystal oscillator producing an interrupt timeout every 3.9718ms, followed 15.5µs later by a watchdog reset.
PAGE 42
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers External/Hardware Reset A hardware reset can be initiated by asserting the RST pin high for at least three external clock cycles while the external clock is running. The reset is asserted immediately. When the RST pin is taken to a logic low, the microcontroller exits the reset state within a delay that depends on the state of the flash memory at the time the reset was asserted.
PAGE 43
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Serial ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is selected, and require the switchback function to automatically return to the divide-by-1 mode for proper operation when a qualified event occurs. Table 15 summarizes the effect of clock mode on timer operation.
PAGE 44
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers Stop Mode Stop mode disables all circuits within the processor. All on-chip clocks, timers, and serial port communication are stopped, and no processing is possible. Stop mode is invoked by setting the stop bit (PCON.1) to logic 1. The processor enters stop mode on the instruction that sets the bit. The processor can exit stop mode by using any of the six external interrupts that are enabled.
PAGE 45
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers PIN CONFIGURATIONS TOP VIEW 1 6 40 7 39 DS89C430 DS89C440 DS89C450 17 P1.0/T2 P1.1/T2EX P1.2/RXD1 P1.3/TXD1 P1.4/INT2 P1.5/INT3 P1.6/INT4 P1.7/INT5 RST P3.0/RXD0 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.
PAGE 46
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) Note: Dimensions are in inches. PKG 40-PIN PDIP DIM MIN MAX A — 0.200 A1 0.015 — A2 0.140 0.160 B 0.014 0.022 C 0.008 0.012 D 1.980 2.085 E 0.600 0.625 E1 0.530 0.555 E 0.090 0.110 L 0.115 0.145 EB 0.600 0.
PAGE 47
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) NOTE 1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. NOTE 2: CONTROLLING DIMENSION ARE IN INCHES.
PAGE 48
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied.