Instruction Manual

Maxim/Dallas Semiconductor Confidential Product Preview: DS3181,2,3,4
Rev 1.5 10 of 13 022304
• Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode or the G.751 Sn bit or the
G.832 NR or GC channels
3.17 FEAC Controller Features
• Designed to handle multiple FEAC codewords without Host intervention
• Receive FEAC automatically validates incoming codewords and stores them in a 4-codeword FIFO
• Transmit FEAC can be configured to send one codeword, one codeword continuously, or two
different codewords back-to-back to send DS3 Line Loopback commands
• Terminates the FEAC channel in DS3 C-Bit Parity mode or the Sn bit in E3 mode
3.18 Trail Trace Buffer Features
• Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register
• Insertion of the outgoing trail access point identifier from a 16-byte transmit register
• Receive trace identifier unstable status indication
3.19 Bit Error Rate Tester (BERT) Features
• Generates and detects pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
• Supports pattern insertion/extraction in PLCP payload, DS3/E3 payload, or entire data stream
• Large 24-bit error counter allows testing to proceed for long periods without host intervention
• Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or
specific bit-error rates)
3.20 Jitter Attenuator Features
• Fully integrated, requires no external components
• Standards-compliant jitter attenuation/jitter transfer
• Can be inserted into the receive path or the transmit path
• 16-bit buffer depth
3.21 Loopback Features
• Line terminal loopback (transmit to receive)
• Line facility loopback (receive to transmit) with optionally transmitting unframed all-one payload
toward system/trunk interface
• Framer diagnostic loopback (transmit to receive) with optionally transmitting unframed all-one signal
toward line/tributary interface
• Simultaneous line facility loopback and framer diagnostic loopback
• Framer payload loopback (receive to transmit) with optionally transmitting unframed all-one payload
toward system/trunk interface
• System interface loopback (transmit to receive)
3.22 Microprocessor Interface Features
• Multiplexed or non-multiplexed 8 or 16-bit control port
• Intel and Motorola bus compatible
• Global reset input pin
• Global interrupt output pin
• Two programmable I/O pins per port