Manual

DS3170 DS3/E3 Single-Chip Transceiver
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9.11.2
Features ............................................................................................................................................. 108
9.11.3 Configuration and Monitoring ............................................................................................................. 108
9.11.4 Receive Pattern Detection ................................................................................................................. 109
9.11.5 Transmit Pattern Generation.............................................................................................................. 111
9.12 LIU – LINE INTERFACE UNIT ........................................................................................................................ 112
9.12.1 General Description ........................................................................................................................... 112
9.12.2 Features ............................................................................................................................................. 112
9.12.3 Detailed Description ........................................................................................................................... 112
9.12.4 Transmitter ......................................................................................................................................... 113
9.12.5 Receiver ............................................................................................................................................. 114
10 OVERALL REGISTER MAP 117
11 REGISTER MAPS AND DESCRIPTIONS 119
11.1 REGISTERS BIT MAPS.................................................................................................................................. 119
11.1.1 Global Register Bit Map ..................................................................................................................... 119
11.1.2 HDLC Register Bit Map...................................................................................................................... 121
11.1.3 T3 Register Bit Map ........................................................................................................................... 123
11.1.4 E3 G.751 Register Bit Map ................................................................................................................ 124
11.1.5 E3 G.832 Register Bit Map ................................................................................................................ 125
11.2 GLOBAL REGISTERS .................................................................................................................................... 126
11.2.1 Register Bit Descriptions.................................................................................................................... 126
11.3 PORT REGISTER.......................................................................................................................................... 133
11.3.1 Register Bit Descriptions.................................................................................................................... 133
11.4 BERT......................................................................................................................................................... 144
11.4.1 BERT Register Map ........................................................................................................................... 144
11.4.2 BERT Register Bit Descriptions ......................................................................................................... 144
11.5 B3ZS/HDB3 LINE ENCODER/DECODER ....................................................................................................... 151
11.5.1 Transmit Side Line Encoder/Decoder Register Map ......................................................................... 151
11.5.2 Receive Side Line Encoder/Decoder Register Map .......................................................................... 152
11.6 HDLC......................................................................................................................................................... 156
11.6.1 HDLC Transmit Side Register Map.................................................................................................... 156
11.6.2 HDLC Receive Side Register Map..................................................................................................... 159
11.7 FEAC CONTROLLER ................................................................................................................................... 163
11.7.1 FEAC Transmit Side Register Map.................................................................................................... 163
11.7.2 FEAC Receive Side Register Map..................................................................................................... 165
11.8 TRAIL TRACE............................................................................................................................................... 168
11.8.1 Trail Trace Transmit Side................................................................................................................... 168
11.8.2 Trail Trace Receive Side Register Map ............................................................................................. 169
11.9 DS3/E3 FRAMER......................................................................................................................................... 174
11.9.1 Transmit DS3 ..................................................................................................................................... 174
11.9.2 Receive DS3 Register Map................................................................................................................ 176
11.9.3 Transmit G.751 E3 ............................................................................................................................. 183
11.9.4 Receive G.751 E3 Register Map ....................................................................................................... 186
11.9.5 Transmit G.832 E3 Register Map ...................................................................................................... 191
11.9.6 Receive G.832 E3 Register Map ....................................................................................................... 194
12 JTAG INFORMATION 202
12.1 JTAG DESCRIPTION.................................................................................................................................... 202
12.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................................. 203
12.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ...................................................................................... 205
12.4 JTAG ID CODES......................................................................................................................................... 206
12.5 JTAG FUNCTIONAL TIMING.......................................................................................................................... 207
12.6 IO PINS ...................................................................................................................................................... 207
13 PIN CONFIGURATIONS 208
14 PACKAGE INFORMATION 213
15 PACKAGE THERMAL INFORMATION 215
16 DC ELECTRICAL CHARACTERISTICS 216
17 AC TIMING CHARACTERISTICS 218