Manual

DS3170 DS3/E3 Single-Chip Transceiver
58 of 233
Table 9-3
identifies the source of the output signal TLCLK based on certain variables and register bits.
Table 9-3. Source Selection of TLCLK Clock Signal
SIGNAL
LOOPT
(PORT.
CR3)
LBM[2:0]
(PORT.CR4
)
LLB or
PLB
LIUEN
CLADC
(PORT.CR3)
SOURCE
1 XXX NA 1 X Rx LIU
1 XXX NA 0 X RLCLK
0 010 LLB 1 X Rx LIU
0 110 LLB 1 X Rx LIU
0 010 LLB 0 X RLCLK
0 110 LLB 0 X RLCLK
0 011 PLB 1 X Rx LIU
0 011 PLB 0 X RLCLK
0 000 NO X 0 CLAD
0 001 NO X 0 CLAD
0 100 NO X 0 CLAD
0 10X NO X 0 CLAD
0 111 NO X 0 CLAD
0 000 NO X 1 TCLKI
0 001 NO X 1 TCLKI
0 100 NO X 1 TCLKI
0 10X NO X 1 TCLKI
TLCLK
0 111 NO X 1 TCLKI
Figure 9-2
shows the source of the TCLKO signals.
Figure 9-2. Internal Tx Clock
0
1
0
1
CLAD
TCLKI
PORT.CR3.
CLADC
RCLKO
PAYLOAD
LOOPBACK
TCLKO
Table 9-4
identifies the source of the output signal TCLKO based on certain variables and register bits.