Manual

DS3170 DS3/E3 Single-Chip Transceiver
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TABLE OF CONTENTS
1 BLOCK DIAGRAMS 2
2 APPLICATIONS 12
3 FEATURE DETAILS 13
3.1 GLOBAL FEATURES........................................................................................................................................ 13
3.2 RECEIVE DS3/E3 LIU FEATURES .................................................................................................................. 13
3.3 JITTER ATTENUATOR FEATURES..................................................................................................................... 13
3.4 RECEIVE DS3/E3 FRAMER FEATURES ........................................................................................................... 13
3.5 TRANSMIT DS3/E3 FORMATTER FEATURES.................................................................................................... 14
3.6 TRANSMIT DS3/E3 LIU FEATURES................................................................................................................. 14
3.7 CLOCK RATE ADAPTER FEATURES ................................................................................................................. 14
3.8 HDLC CONTROLLER FEATURES..................................................................................................................... 14
3.9 FEAC CONTROLLER FEATURES..................................................................................................................... 14
3.10 TRAIL TRACE BUFFER FEATURES ................................................................................................................... 15
3.11 BIT ERROR-RATE TESTER (BERT) FEATURES................................................................................................ 15
3.12 LOOPBACK FEATURES ................................................................................................................................... 15
3.13 MICROPROCESSOR INTERFACE FEATURES ..................................................................................................... 15
3.14 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ................................................................................ 15
3.15 TEST FEATURES............................................................................................................................................ 15
4 STANDARDS COMPLIANCE 16
5 ACRONYMS AND GLOSSARY 17
6 MAJOR OPERATIONAL MODES 18
6.1 DS3/E3 FRAMED LIU MODE.......................................................................................................................... 18
6.2 DS3/E3 UNFRAMED LIU MODE ..................................................................................................................... 20
6.3 DS3/E3 FRAMED POS/NEG MODE............................................................................................................... 21
6.4 DS3/E3 UNFRAMED POS/NEG MODE .......................................................................................................... 22
6.5 DS3/E3 FRAMED UNI MODE ......................................................................................................................... 23
6.6 DS3/E3 UNFRAMED UNI MODE..................................................................................................................... 24
7 PIN DESCRIPTIONS 25
7.1 SHORT PIN DESCRIPTIONS............................................................................................................................. 25
7.2 DETAILED PIN DESCRIPTIONS......................................................................................................................... 27
7.3 PIN FUNCTIONAL TIMING ................................................................................................................................37
7.3.1 Line IO.................................................................................................................................................. 37
7.3.2 DS3/E3 Framing Overhead Functional Timing .................................................................................... 40
7.3.3 DS3/E3 Serial Data Interface............................................................................................................... 41
7.3.4 Microprocessor Interface Functional Timing ........................................................................................ 43
7.3.5 JTAG Functional Timing....................................................................................................................... 50
8 INITIALIZATION AND CONFIGURATION 51
8.1 MONITORING AND DEBUGGING ....................................................................................................................... 52
9 FUNCTIONAL DESCRIPTION 53
9.1 PROCESSOR BUS INTERFACE......................................................................................................................... 53
9.1.1 SPI Serial Port Mode............................................................................................................................ 53
9.1.2 8/16 Bit Bus Widths.............................................................................................................................. 53
9.1.3 Ready Signal ( RDY ) ............................................................................................................................. 53
9.1.4 Byte Swap Modes ................................................................................................................................ 53
9.1.5 Read-Write/Data Strobe Modes ........................................................................................................... 53
9.1.6 Clear on Read/Clear on Write Modes .................................................................................................. 53
9.1.7 Interrupt and Pin Modes....................................................................................................................... 54
9.1.8 Interrupt Structure ................................................................................................................................ 54
9.2 CLOCKS ........................................................................................................................................................ 55
9.2.1 Line Clock Modes................................................................................................................................. 55
9.2.2 Sources of Clock Output Pin Signals ................................................................................................... 57
9.2.3 Line IO Pin Timing Source Selection ................................................................................................... 59
9.2.4 Clock Structures On Signal IO Pins ..................................................................................................... 62