Manual

DS3170 DS3/E3 Single-Chip Transceiver
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Bit 3: Remote Defect Indication Interrupt Enable (RDIIE) – This bit enables an interrupt if the RDIL bit is set and
the bit in GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Alarm Indication Signal Interrupt Enable (AISIE) – This bit enables an interrupt if the AISL bit is set and
the bit in GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Out Of Frame Interrupt Enable (OOFIE) – This bit enables an interrupt if the OOFL bit is set and the bit in
GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Loss Of Signal Interrupt Enable (LOSIE) – This bit enables an interrupt if the LOSL bit is set and the bit in
GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Register Name:
T3.RSRIE2
Register Description:
T3 Receive Status Register Interrupt Enable #2
Register Address:
12Eh
Bit # 15 14 13 12 11 10 9 8
Name -- -- -- -- CPEIE FBEIE PEIE FEIE
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Name -- -- -- -- CPECIE FBECIE PECIE FECIE
Default 0 0 0 0 0 0 0 0
Bit 11: C-bit Parity Error Interrupt Enable (CPEIE) – This bit enables an interrupt if the CPEL bit is set and the bit
in GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 10: Remote Error Interrupt Enable (FBEIE) – This bit enables an interrupt if the FBEL bit is set and the bit in
GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 9: P-bit Parity Error Interrupt Enable (PEIE) – This bit enables an interrupt if the PEL bit is set and the bit in
GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 8: Framing Error Interrupt Enable (FEIE) – This bit enables an interrupt if the FEL bit is set and the bit in
GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: C-bit Parity Error Count Interrupt Enable (CPECIE) – This bit enables an interrupt if the CPECL bit is set
and the bit in GL.ISRIE
.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled