Manual

DS3170 DS3/E3 Single-Chip Transceiver
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11.5 B3ZS/HDB3 Line Encoder/Decoder
11.5.1 Transmit Side Line Encoder/Decoder Register Map
The transmit side utilizes one register.
Table 11-14. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map
Address Register Register Description
08Ch LINE.TCR
Line Transmit Control Register
08Eh -- Unused
11.5.1.1 Register Bit Descriptions
Register Name:
LINE.TCR
Register Description:
Line Transmit Control Register
Register Address:
08Ch
Bit # 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Name -- -- -- TZSD EXZI BPVI TSEI MEIMS
Default 0 0 0 0 0 0 0 0
Bit 4: Transmit Zero Suppression Encoding Disable (TZSD) – When 0, the B3ZS/HDB3 Encoder performs zero
suppression (B3ZS or HDB3) and AMI encoding. When 1, zero suppression (B3ZS or HDB3) encoding is disabled,
and only AMI encoding is performed.
Bit 3: Excessive Zero Insert Enable (EXZI) – When 0, excessive zero (EXZ) event insertion is disabled. When 1,
EXZ event insertion is enabled.
Bit 2: Bipolar Violation Insert Enable (BPVI) – When 0, bipolar violation (BPV) insertion is disabled. When 1,
BPV insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) – This bit causes an error of the enabled type(s) to be inserted in the
transmit data stream if manual error insertion is disabled (MEIMS = 0). A 0 to 1 transition causes a single error to
be inserted. For a second error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and
this bit transitions more than once between error insertion opportunities, only one error will be inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause an error to be inserted.