Manual

DS3170 DS3/E3 Single-Chip Transceiver
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Register Name:
BERT.RBECR1
Register Description:
BERT Receive Bit Error Count Register #1
Register Address:
074h
Bit # 15 14 13 12 11 10 9 8
Name BEC15
BEC14 BEC13 BEC12 BEC11 BEC10 BEC9 BEC8
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Name BEC7
BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BEC0
Default 0 0 0 0 0 0 0 0
Bits 15 to 0: Bit Error Count (BEC[15:0]) – Lower sixteen bits of 24 bits. Register description follows next
register.
Register Name:
BERT.RBECR2
Register Description:
BERT Receive Bit Error Count Register #2
Register Address:
076h
Bit # 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Name BEC23
BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC16
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Bit Error Count (BEC[23:16]) - Upper 8-bits of Register.
Bit Error Count (BEC[23:0]) – These twenty-four bits indicate the number of bit errors detected in the incoming
data stream. This count stops incrementing when it reaches a count of FF FFFFh. This bit error counter will not
increment when an OOS condition exists. This register is updated via the PMU signal (see section 9.4.5
)