Instruction Manual

Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4
Rev 1.6 7 of 12 022604
• Programmable fill level thresholds
• Underflow and overflow status indications
3.7 Receive System Interface Features
• UTOPIA 2 / UTOPIA 3 interface in cell mode, POS-PHY 2 / POS-PHY 3 interface in packet or
mixed traffic modes
• 8, 16, or 32 bit data bus at clock rates from 10 MHz to 66 MHz
• Polled and direct cell available outputs
• Controls include enables/disables/settings for: HEC transfer, signal inversions, parity enable/polarity,
cell available desertion time
3.8 Transmit System Interface Features
• UTOPIA 2 / UTOPIA 3 interface in cell mode, POS-PHY 2 / POS-PHY 3 interface in packet or
mixed traffic modes
• 8, 16, or 32 bit data bus at clock rates from 10 MHz to 66 MHz
• Polled and direct cell available outputs
• Controls include enables/disables/settings for: HEC transfer, signal inversions, parity enable/polarity,
cell available desertion time
3.9 Transmit FIFO Features
• Storage capacity for four cells or 256 bytes of packet data
• Programmable port address
• Programmable fill level thresholds
• Underflow and overflow status indications
3.10 Transmit Cell Processor Features
• Programmable fill cell type
• HEC calculation and insertion/overwrite, including coset addition
• Cell scrambling using the self-synchronizing scrambler (x
43
+1) for ATM over DS3/E3 or the
distributed sample scrambler for clear-channel ATM (cell-based physical layer)
• Single-bit and multiple-bit header error insertion for diagnostics
• Controls include enables/disables/settings for: cell processing, HEC insertion, coset polynomial
addition, cell scrambling, fill cell type, error insertion type/rate/count, HEC bit corruption
• Counter for number of cells read from the transmit FIFO
• Cell mapping into the DS3/E3 frame, the PLCP frame, an externally defined frame, or the entire line
bandwidth
3.11 Transmit Packet Processor Features
• FCS calculation (16-bit or 32-bit) and insertion/overwrite
• Programmable FCS error insertion for diagnostics
• Bit or octet stuffing
• Programmable inter-frame fill insertion (flags or all-ones)
• Automatic packet abort insertion
• Packet scrambling using the self-synchronizing scrambler (x
43
+1)
• Controls include enables/disables/settings for: packet processing, FCS insertion or overwrite, 16/32-
bit FCS, inter-frame fill type/length, scrambling, FCS error insertion type/rate/count