Instruction Manual

Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4
Rev 1.6 6 of 12 022604
Framer pass-through mode for clear channel applications and externally defined frame formats
Built-in support for subrate DS3/E3
3.3 Receive PLCP Framer Features
PLCP frame synchronization
C1 cycle/stuff counter interpretation
Detection of out of frame (OOF), BIP-8 errors, FEBE and RAI (Yellow Signal)
Frame timing is presented on the 8KREFO output pin
All path overhead fields presented on the PLCP receive overhead port
3.4 Receive Cell Processor Features
HEC-based cell delineation within the DS3/E3 frame, the PLCP frame, an externally defined frame,
or the entire line bandwidth
Cell descrambling using the self-synchronizing scrambler (x
43
+1) for ATM over DS3/E3 or the
distributed sample scrambler for clear-channel ATM (cell-based physical layer)
HEC error detection and correction; HEC discard
Filtering of idle, unassigned and/or invalid cells (provisionable)
Header pattern comparison vs. 32-bit header pattern and mask registers; counting of matching or non-
matching cells; discard of matching or non-matching cells
Four-cell Receive FIFO
Controls include enables/disables/settings for: cell processing, coset polynomial addition, error
correction, erred cell extraction, cell descrambling, idle/unassigned/invalid cell filtering, header
pattern match counting/discarding, LCD integration time
Status fields include: out of cell delineation (OCD), loss of cell delineation (LCD) and receipt of idle,
unassigned, invalid, erred, corrected or header-pattern-match cells
Performance monitoring counters for forwarded cells, corrected cells, uncorrectable cells, header
pattern match/no-match cells, and filtered idle/unassigned/invalid cells
3.5 Receive Packet Processor Features
Packet descrambling using the self-synchronizing scrambler (x
43
+1)
Flag detection, packet delineation, and interframe fill discard (flags and all-ones)
Packet abort detection and accumulation
Bit or octet destuffing
FCS checking (16-bit or 32-bit), error accumulation, and FCS discard
Packet size checking vs. programmable minimum and maximum size registers
Abort declaration for packets with non-integral number of bytes
Controls include enables/disables/settings for: packet processing, descrambling, 16/32-bit FCS,
filtering of FCS erred packets, FCS discard, minimum/maximum packet size
Status fields include: receipt of FCS erred packet, aborted packet, size violation packet, non-integer-
length packets
Performance monitoring counters for forwarded packets, forwarded bytes, aborted bytes, FCS erred
packets, aborted packets, size violation packets (min, max, non-integer-length)
3.6 Receive FIFO Features
Storage capacity for four cells or 256 bytes of packet data
Programmable port address