Instruction Manual
Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4
Rev 1.6 3 of 12 022604
DESCRIPTION
The DS316x Multi-port PHYs map ATM cells and/or packets into as many as four DS3/E3 data streams.
Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission
and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive
cell/packet data in properly formatted M23 DS3, C-bit DS3, G.751 E3 or G.832 E3 data streams. PLCP
framers provide legacy ATM transmission-convergence support. With integrated hardware support for
both cells and packets, the DS316x PHYs enable high-density universal line cards for unchannelized
DS3/E3.
1 BLOCK DIAGRAM
Figure 1–1 Block Diagram
TLCLKn
TSOFn / TIOHMn
TDATn
TDENn / TGCLKn
TPOHn
TPOHGCLKn
TPOHSOFn
8KREFI
TOHn
TOHGCLKn
TOHSOFn
TMEI
System
Interface
TSCLK
TADR
[
4:0
]
TDATA
[
31:0
]
TPRTY*
TEN*
TPX
A
TDXA
[
4:1
]
TSOX
TEOP
TSX
TMOD
[
1:0
]
TERR
TSP
A
Tx
FIFO
Tx
PLCP/DSS/FRAC
Formatter
Tx Cell
Processor
TPOSn / TNRZn DS3 / E3
Transmit
Formatter
B3ZS/
HDB3
Encoder
TNEGn / TOHMn
Tx Packet
Processor
TCLKn
Framer Diagnostic
Loopback
System Interface
Loopback
Line Facility Loopback
Framer Payload
Loopback
Trail
Trace
Buffer
HDLC
FEAC
BERT
RSCLK
RADR
[
4:0
]
RDATA
[
31:0
]
RPRTY*
REN*
RPX
A
RDXA
[
4:1
]
RSOX
REOP
RSX
RVAL
RMOD
[
1:0
]
RERR
Rx
FIFO
Rx Packet
Processor
DS3 / E3
Receive
Framer
B3ZS/
HDB3
Decoder
RPOSn / RNRZn
Rx
PLCP/DSS/FRAC
Framer
Rx Cell
Processor
RNEGn / RLCVn / ROHMn
RCLKn
Microprocessor
Interface
IEEE P1149.1
JTAG Test
Access Port
Clock
Rate
Adapter
n = port #
CLK
A
CLKB
REFCL
K
RDATn
RDENn / RGCLKn
RSOFn
RLCLKn
ROHn
RECU
ROHGCLKn
ROHSOFn
JTDO
JTDI
JTCL
K
JTRST*
JTMS
RPOHn
RPOHGCLKn
RPOHSOFn
8KREFO
ALE
CS*
RD*/DS*
WR*/ R/W*
MOT
RST*
INT*
PIOAn
PIOBn
D
[
15:0
]
A
[
9:0
]
2 APPLICATIONS
• Access Concentrators
• Multi-Service Access Platforms
• ATM and Frame Relay Equipment
• Routers and Switches
• SONET/SDH ADM
• Digital Cross Connect
• PDH Multiplexer/Demultiplexer