User guide

DS3134

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76543210

RHPL7 RHPL6 RHPL5 RHPL4 RHPL3 RHPL2 RHPL1 RHPL0

15 14 13 12 11 10 9 8

RHPL15 RHPL14 RHPL13 RHPL12 RHPL11 RHPL10 RHPL9 RHPL8

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0s.

This is a globe control only one per device and it is not one for each individual HDLC channel.

Bits 0 to 15 / Receive HDLC Packet Length (RHPL0 to RHPL15). If the Receive Length Detection

Enable bit is set to one, then the HDLC engine will check the number of received octets in a packet to see

if they exceed the count in this register. If the length is exceeded, then the packet is aborted and the

remainder is discarded. The definition of "octet length" is everything in between the opening and closing

flags which includes the address field, control field, information field, and FCS.

76543210

HCID7 HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0

15 14 13 12 11 10 9 8

IAB IARW n/a n/a n/a n/a n/a n/a

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.

Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).

00000000 (00h) = HDLC Channel Number 1 (also used for the Fast HDLC Engine on Port 0)

00000001 (01h) = HDLC Channel Number 2 (also used for the Fast HDLC Engine on Port 1)

00000010 (02h) = HDLC Channel Number 3

11111111 (FFh) = HDLC Channel Number 256

Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal

Transmit HDLC Definition RAM, this bit should be written to a one by the host. This causes the device

to begin obtaining the data from the channel location indicated by the HCID bits. During the read access,

the IAB bit will be set to one. Once the data is ready to be read from the THCD register, the IAB bit will

be set to zero. When the host wishes to write data to the internal Transmit HDLC Definition RAM, this

bit should be written to a zero by the host. This causes the device to take the data that is current present in

the THCD register and write it to the channel location indicated by the HCID bits. When the device has

completed the write, the IAB will be set to zero.

Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only

bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be

read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set

to a one while the write is taking place. It will be set to zero once the write operation has completed.