User guide

DS3134
197 of 203
AC CHARACTERISTICS - JTAG TEST PORT INTERFACE
(0°C TO +70°C; VDD = 3.0V TO 3.6V)
Parameter Symbol Min Typ Max Units Notes
JTCLK Clock Period t1 1000 ns
JTCLK Clock Low Time t2 400 ns
JTCLK Clock High Time t3 400 ns
JTMS / JTDI Set Up Time to the
Rising Edge of JTCLK
t4 50 ns
JTMS / JTDI Hold Time from the
Rising Edge of JTCLK
t5 50 ns
Delay Time from the Falling Edge of
JTCLK to Data Valid on JTDO
t6 2 50 ns
JTAG TEST PORT INTERFACE AC TIMING DIAGRAM Figure 12E
JTCLK
JTMS / JTDI
JTDO
t4 t5
t6
t1
t2 t3
jtag_ac