User guide
DS3134
143 of 203
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 3; Bits 16 to 31 / Last Pending Descriptor Pointer. This 16-bit value is the offset from the
Transmit Descriptor Base Address of the first Transmit Packet Descriptor for the packet that is queued up
last for transmission.
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 4; Bits 0 to 15 / Next Priority Descriptor Pointer. This 16-bit value is the offset from the
Transmit Descriptor Base Address of the next Transmit Priority Packet Descriptor for the priority packet
that is currently being transmitted. Only valid if EOF = 0 or if EOF = 1 and CV = 1.
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 4; Bits 16 to 31/ Unused. This field is not used by the DMA and could be any value when read.
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 5; Bits 0 to 15 / Last Priority Pending Descriptor Pointer. This 16-bit value is the offset from
the Transmit Descriptor Base Address of the first Transmit Priority Packet Descriptor for the priority
packet that is queued up last for transmission.
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 5; Bits 16 to 31 / Next Priority Pending Descriptor Pointer. This 16-bit value is the offset from
the Transmit Descriptor Base Address of the first Transmit Priority Packet Descriptor for the packet
priority that is queued up next for transmission.
Register Name: TDMACIS
Register Description: Transmit DMA Configuration Indirect Select
Register Address: 0870h
76543210
HCID7 HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0
15 14 13 12 11 10 9 8
IAB IARW n/a n/a TDCW3 TDCW2 TDCW1 TDCW0
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256










