User guide

DS3134
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- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 2; Bits 29 to 31 / Threshold Count. These 3 bits keep track of the number of data buffers that
have been filled so that the Receive DMA knows when to write to the Done Queue based on the Host
controlled field called Threshold.
000 = threshold count is 0 data buffers
001 = threshold count is 1 data buffer
010 = threshold count is 2 data buffers
011 = threshold count is 3 data buffers
100 = threshold count is 4 data buffers
101 = threshold count is 5 data buffers
110 = threshold count is 6 data buffers
111 = threshold count is 7 data buffers
Register Name: RDMACIS
Register Description: Receive DMA Channel Configuration Indirect Select
Register Address: 0770h
76543210
HCID7 HCID6 HCID5 HCID4 HCID3 HCID2 HCID1 HCID0
15 14 13 12 11 10 9 8
IAB IARW n/a n/a n/a RDCW2 RDCW1 RDCW0
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256
Bits 8 to 10 / Receive DMA Configuration RAM Word Select Bits 0 to 2 (RDCW0 to RDCW2).
000 = lower word of dword 0
001 = upper word of dword 0
010 = lower word of dword 1
011 = upper word of dword 1
100 = lower word of dword 2 (only word that the Host can write to)
101 = upper word of dword 2
110 = illegal state
111 = illegal state
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Receive DMA Configuration RAM, this bit should be written to a one by the host. This causes the device
to begin obtaining the data from the channel location indicated by the HCID bits. During the read access,
the IAB bit will be set to one. Once the data is ready to be read from the RDMAC register, the IAB bit
will be set to zero. When the host wishes to write data to the internal Receive DMA Configuration RAM,
this bit should be written to a zero by the host. This causes the device to take the data that is current
present in the RDMAC register and write it to the channel location indicated by the HCID bits. When the
device has completed the write, the IAB bit will be set to zero.