Owner's manual

DS3131

96 of 174

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive DMA

configuration RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data

from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data

is ready to be read from the RDMAC register, the IAB bit is set to 0. When the host wishes to write data to the

internal receive DMA configuration RAM, this bit should be written to 0 by the host. This causes the device to

take the data that is currently present in the RDMAC register and write it to the channel location indicated by the

HCID bits. When the device has completed the write, the IAB bit is set to 0.

Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set

to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is

ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the

write operation has completed.

Bit # 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0

Default

Bit # 15 14 13 12 11 10 9 8

Name D15 D14 D13 D12 D11 D10 D9 D8

Default

Note: Bits that are underlined are read-only, all other bits are read-write.

Bits 0 to 15/Receive DMA Configuration RAM Data (D0 to D15). Data that is written to or read from the

Receive DMA Configuration RAM.