Owner's manual

DS3131
7 of 174
Table 1-A. Data Sheet Definitions
The following terms are used throughout this data sheet.
Note: The DS3131’s ports are numbered 0 to 39; the HDLC channels are numbered 1 to 40. HDLC Channel 1 is always associated with Port
0, HDLC Channel 2 with Port 1, and so on.
TERM DEFINITION
BERT Bit Error-Rate Tester
Descriptor A message passed back and forth between the DMA and the host
Dword Double word; a 32-bit data entity
DMA Direct Memory Access
FIFO First In, First Out. A temporary memory storage scheme.
HDLC High-Level Data-Link Control
Host The main controller that resides on the PCI Bus
n/a Not assigned
2. DETAILED DESCRIPTION
The DS3131 BoSS HDLC controller is based on Dallas Semiconductor’s DS3134 CHATEAU HDLC
controller. Both devices share the same DMA and FIFO structure as well as the same signal locations for
the local bus and the PCI bus. The primary difference between the two devices is in the Layer 1
functionality. The CHATEAU supports channelized T1/E1 whereas the BoSS does not. Therefore, the
Layer 1 functions in the CHATEAU that support channelized interfaces do not exist in the BoSS.
Figure 2-1 shows the major blocks of the device. The DS3131 can be operated in two configurations
depending on whether the local bus is enabled or not (Figure 2-2).
The Layer 1 block handles the physical input and output of serial data to and from the DS3131. The
DS3131 is capable of operating in a number of modes and can be used in many applications requiring
high-density and high-speed HDLC termination. Section 15 details a few common applications for the
DS3131. The Layer 1 block prepares the incoming data for the HDLC block and grooms data from the
HDLC block for transmission. The Layer 1 block interfaces directly to the BERT block. The BERT
block can generate and detect both pseudorandom and repeating bit patterns and is used to test and stress
data communication links. The BERT block is a global chip resource that can be assigned to any one of
the 40 bit-synchronous ports.
The DS3131 BoSS is composed of 40 bit-synchronous HDLC controllers (one for each port) that are
each capable of operating at speeds up to 52Mbps. The bit-synchronous HDLC controllers also have
serial interfaces. The HDLC controllers perform all of the Layer 2 processing, which includes zero
stuffing and destuffing, flag generation and detection, CRC generation and checking, and abort
generation and checking.
In the receive path, the following process occurs. The HDLC controllers collect the incoming data and
then signal the FIFO that the controller has data to transfer. The 40 ports are priority decoded (Port 0 gets
the highest priority) for the data transfer from the HDLC controllers to the FIFO block. There is no
priority of transfer between the HDLC controllers and the FIFO because the DS3131 handles up to
132Mbps in both the receive and the transmit directions without any potential data loss because of
priority conflicts.