Owner's manual

DS3131
50 of 174
Transmit Side Control Bits (one each for all 40 ports)
Register Name: TP[n]CR, where n = 0 to 39 for each port
Register Description: Transmit Port [n] Control Register
Register Address: See the Register Map in Section 4
.
Bit # 7 6 5 4 3 2 1 0
Name reserved reserved reserved reserved TFDA1 reserved TIDE TICE
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Name reserved reserved reserved reserved TBS PLB reserved reserved
Default 0 0 0 0 0 0 0 0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Invert Transmit Clock Enable (TICE)
0 = do not invert clock (normal clock mode)
1 = invert clock (inverted clock mode)
Bit 1/Invert Transmit Data Enable (TIDE)
0 = do not invert data (normal data mode)
1 = invert data (inverted data mode)
Bit 3/Force Data All Ones (TFDA1)
0 = force all data at TD to be 1
1 = allow data to be transmitted normally
Bit 10/Port Loopback Enable (PLB). This loopback routes the data incoming at the RD pin to the TD pin
(Figure 6-1
).
0 = loopback disabled
1 = loopback enabled
Bit 11/BERT Select (TBS). This select bit controls whether data is to be sourced from the HDLC controller or
from the BERT block (Figure 6-1
). See Section 6.3 for details on how to configure the operation of the BERT.
0 = source transmit data from the HDLC controller
1 = source transmit data from the BERT block