Owner's manual

DS3131
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for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal
pin and also at the LINT if the local bus is in configuration mode.
Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE). This status bit is set to 1 each time
the receive DMA tries to write to the done queue and it is full. The RDQWE bit is cleared when read and is not set
again until another write to the done queue detects that it is full. If enabled through the RDQWE bit in the interrupt
mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA
signal pin and also at the LINT if the local bus is in configuration mode.
Bit 12/Status Bit for Transmit FIFO Underflow (TUDFL). This status bit is set to 1 if any of the HDLC
channels experiences an underflow in the transmit FIFO. The TUDFL bit is cleared when read and is not set again
until another underflow has occurred. If enabled through the TUDFL bit in the interrupt mask for SDMA
(ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also
at the LINT if the local bus is in configuration mode.
Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR). This status bit is set to 1 each time the
transmit DMA reads the pending queue. The TPQR bit is cleared when read and is not set again until another read
of the pending queue has occurred. If enabled through the TPQR bit in the interrupt mask for SDMA (ISDMA),
the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT
if the local bus is in configuration mode.
Bit 14/Status Bit for Transmit DMA Done-Queue Write (TDQW). This status bit is set to 1 when the transmit
DMA writes to the done queue. Based on the setting of the transmit done-queue threshold setting (TDQT0 to
TDQT2) bits in the transmit DMA queues-control (TDMAQ) register, this bit is set either after each write or after
a programmable number of writes from 2 to 128 (Section 9.2.4
). The TDQW bit is cleared when read and is not set
again until another write to the done queue has occurred. If enabled through the TDQW bit in the interrupt mask
for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal
pin and also at the LINT if the local bus is in configuration mode.
Bit 15/Status Bit for Transmit DMA Done-Queue Write Error (TDQWE). This status bit is set to 1 each time
the transmit DMA tries to write to the done queue and it is full. The TDQWE bit is cleared when read and is not
set again until another write to the done queue detects that it is full. If enabled through the TDQWE bit in the
interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the
PINTA signal pin and also at the LINT if the local bus is in configuration mode.