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Figure 5-1. Status Register Block Diagram for SM
OR
SBERT
PSERRPPERR
n/an/aLBINT LBE
BERTEC0 Bit 1 (BECO)
BERTEC0 Bit 2 (BBCO)
BERTC0 Bit 13 (IEOF)
Change in BERTEC0 Bit 0 (SYNC)
BERTC0 Bit 15 (IESYNC)
BERTEC0 Bit 3 (BED)
BERTC0 Bit 14 (IEBED)
OR
BERT
SM: STATUS MASTER REGISTE
n/a n/a
