Owner's manual

DS3131
4 of 174
LIST OF FIGURES
Figure 2-1. Block Diagram ........................................................................................................................10
Figure 2-2. Configuration Options.............................................................................................................11
Figure 3-1. Signal Floorplan ......................................................................................................................19
Figure 5-1. Status Register Block Diagram for SM...................................................................................40
Figure 6-1. Layer 1 Port Interface Block Diagram ....................................................................................48
Figure 6-2. BERT Mux Diagram ...............................................................................................................51
Figure 6-3. BERT Register Set ..................................................................................................................52
Figure 8-1. FIFO Example.........................................................................................................................66
Figure 9-1. Receive DMA Operation.........................................................................................................78
Figure 9-2. Receive DMA Memory Organization.....................................................................................79
Figure 9-3. Receive Descriptor Example...................................................................................................80
Figure 9-4. Receive Packet Descriptors.....................................................................................................81
Figure 9-5. Receive Free-Queue Descriptor ..............................................................................................82
Figure 9-6. Receive Free-Queue Structure ................................................................................................84
Figure 9-7. Receive Done-Queue Descriptor.............................................................................................87
Figure 9-8. Receive Done-Queue Structure...............................................................................................89
Figure 9-9. Receive DMA Configuration RAM ........................................................................................93
Figure 9-10. Transmit DMA Operation .....................................................................................................99
Figure 9-11. Transmit DMA Memory Organization ...............................................................................100
Figure 9-12. Transmit DMA Packet Handling.........................................................................................101
Figure 9-13. Transmit DMA Priority Packet Handling ...........................................................................102
Figure 9-14. Transmit DMA Error Recovery Algorithm.........................................................................104
Figure 9-15. Transmit Descriptor Example .............................................................................................105
Figure 9-16. Transmit Packet Descriptors ...............................................................................................106
Figure 9-17. Transmit Pending-Queue Descriptor...................................................................................107
Figure 9-18. Transmit Pending-Queue Structure.....................................................................................109
Figure 9-19. Transmit Done-Queue Descriptor .......................................................................................111
Figure 9-20. Transmit Done-Queue Structure .........................................................................................113
Figure 9-21. Transmit DMA Configuration RAM...................................................................................116
Figure 10-1. PCI Configuration Memory Map........................................................................................121
Figure 10-2. PCI Bus Read ......................................................................................................................122
Figure 10-3. PCI Bus Write .....................................................................................................................123
Figure 10-4. PCI Bus Arbitration Signaling Protocol..............................................................................124
Figure 10-5. PCI Initiator Abort ..............................................................................................................124
Figure 10-6. PCI Target Retry .................................................................................................................125
Figure 10-7. PCI Target Disconnect ........................................................................................................125
Figure 10-8. PCI Target Abort.................................................................................................................126
Figure 10-9. PCI Fast Back-to-Back........................................................................................................127
Figure 11-1. Bridge Mode........................................................................................................................139
Figure 11-2. Bridge Mode with Arbitration Enabled...............................................................................139
Figure 11-3. Configuration Mode ............................................................................................................140
Figure 11-4. Local Bus Access Flowchart...............................................................................................144
Figure 11-5. 8-Bit Read Cycle .................................................................................................................147
Figure 11-6. 16-Bit Write Cycle ..............................................................................................................148
Figure 11-7. 8-Bit Read Cycle .................................................................................................................149
Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle .................................................................150