Owner's manual

DS3131
3 of 174
9.2.4 Done Queue.........................................................................................................................................87
9.2.5 DMA Configuration RAM ...................................................................................................................93
9.3 TRANSMIT SIDE........................................................................................................................................97
9.3.1 Overview .............................................................................................................................................97
9.3.2 Packet Descriptors............................................................................................................................105
9.3.3 Pending Queue..................................................................................................................................107
9.3.4 Done Queue.......................................................................................................................................111
9.3.5 DMA Configuration RAM .................................................................................................................116
10. PCI BUS ........................................................................................................................................ 121
10.1 GENERAL DESCRIPTION OF OPERATION................................................................................................121
10.1.1 PCI Read Cycle.................................................................................................................................122
10.1.2 PCI Write Cycle ................................................................................................................................123
10.1.3 PCI Bus Arbitration ..........................................................................................................................124
10.1.4 PCI Initiator Abort............................................................................................................................124
10.1.5 PCI Target Retry...............................................................................................................................125
10.1.6 PCI Target Disconnect......................................................................................................................125
10.1.7 PCI Target Abort...............................................................................................................................126
10.1.8 PCI Fast Back-to-Back......................................................................................................................127
10.2 PCI CONFIGURATION REGISTER DESCRIPTION .....................................................................................128
10.2.1 Command Bits...................................................................................................................................129
10.2.2 Status Bits..........................................................................................................................................130
10.2.3 Command Bits...................................................................................................................................134
10.2.4 Status Bits..........................................................................................................................................135
11. LOCAL BUS................................................................................................................................. 138
11.1 GENERAL DESCRIPTION.........................................................................................................................138
11.1.1 PCI Bridge Mode ..............................................................................................................................141
11.1.2 Configuration Mode..........................................................................................................................143
11.2 LOCAL BUS BRIDGE MODE CONTROL REGISTER DESCRIPTION............................................................145
11.3 EXAMPLES OF BUS TIMING FOR LOCAL BUS PCI BRIDGE MODE OPERATION .....................................147
12. JTAG ............................................................................................................................................. 155
12.1 JTAG DESCRIPTION...............................................................................................................................155
12.2 TAP CONTROLLER STATE MACHINE DESCRIPTION..............................................................................156
12.3 INSTRUCTION REGISTER AND INSTRUCTIONS........................................................................................159
12.4 TEST REGISTERS ....................................................................................................................................160
13. AC CHARACTERISTICS .......................................................................................................... 161
14. MECHANICAL DIMENSIONS................................................................................................. 169
14.1 272 PBGA PACKAGE.............................................................................................................................169
15. APPLICATIONS ......................................................................................................................... 170
15.1 T1/E1 AND T3/E3 APPLICATIONS..........................................................................................................170
15.2 DSL AND CABLE MODEM APPLICATIONS .............................................................................................173
15.3 SONET/SDH APPLICATIONS ................................................................................................................174