Owner's manual

DS3131
28 of 174
4. MEMORY MAP
4.1 Introduction
All addresses within the memory map are on dword boundaries, even though all internal device
configuration registers are only one word (16 bits) wide. The memory map consumes an address range of
4kb (12 bits). When the PCI bus is the host (i.e., the local bus is in bridge mode), the actual 32-bit PCI
bus addresses of the internal device configuration registers are obtained by adding the DC base address
value in the PCI device-configuration memory-base address register (Section 10.2) to the offset listed in
Sections 4.1 to 4.10. When an external host is configuring the device through the local bus (i.e., the local
bus is in the configuration mode), the offset is 0h and the host on the local bus uses the 16-bit addresses
listed in Sections 4.2 to 4.10.
Table 4-A. Memory Map Organization
REGISTER
PCI HOST [OFFSET
FROM DC BASE]
LOCAL BUS HOST
(16-BIT ADDRESS)
SECTION
General Configuration Registers (0x000) (00xx) 4.2
Receive Port Registers (0x1xx) (01xx) 4.3
Transmit Port Registers (0x2xx) (02xx) 4.4
Receive HDLC Control Registers (0x3xx) (03xx) 4.5
Transmit HDLC Control Registers (0x4xx) (04xx) 4.6
BERT Registers (0x5xx) (05xx) 4.7
Receive DMA Registers (0x7xx) (07xx) 4.8
Transmit DMA Registers (0x8xx) (08xx) 4.9
FIFO Registers (0x9xx) (09xx) 4.10
PCI Configuration Registers for Function 0 (PIDSEL) (0Axx) 4.11
PCI Configuration Registers for Function 1 (PIDSEL) (0Bxx) 4.12
4.2 General Configuration Registers (0xx)
OFFSET/
ADDRESS
NAME REGISTER SECTION
0000 MRID Master Reset and ID Register 5.1
0010 MC Master Configuration 5.2
0020 SM Master Status Register 5.3.2
0024 ISM Interrupt Mask Register for SM 5.3.2
0028 SDMA Status Register for DMA 5.3.2
002C ISDMA Interrupt Mask Register for SDMA 5.3.2
0040 LBBMC Local Bus Bridge Mode Control Register 11.2
0050 TEST Test Register 5.4