Owner's manual

DS3131
2 of 174
TABLE OF CONTENTS
1. MAIN FEATURES .......................................................................................................................... 6
2. DETAILED DESCRIPTION.......................................................................................................... 7
3. SIGNAL DESCRIPTION..............................................................................................................14
3.1 OVERVIEW/SIGNAL LIST..........................................................................................................................14
3.2 SERIAL PORT INTERFACE SIGNAL DESCRIPTION .....................................................................................20
3.3 LOCAL BUS SIGNAL DESCRIPTION ..........................................................................................................20
3.4 JTAG SIGNAL DESCRIPTION ...................................................................................................................23
3.5 PCI BUS SIGNAL DESCRIPTION ...............................................................................................................24
3.6 PCI EXTENSION SIGNALS ........................................................................................................................26
3.7 SUPPLY AND TEST SIGNAL DESCRIPTION................................................................................................27
4. MEMORY MAP ............................................................................................................................ 28
4.1 INTRODUCTION ........................................................................................................................................28
4.2 GENERAL CONFIGURATION REGISTERS (0XX) ........................................................................................28
4.3 RECEIVE PORT REGISTERS (1XX) ............................................................................................................29
4.4 TRANSMIT PORT REGISTERS (2XX)..........................................................................................................30
4.5 RECEIVE HDLC CONTROL REGISTERS (3XX) .........................................................................................31
4.6 TRANSMIT HDLC CONTROL REGISTERS (4XX).......................................................................................32
4.7 BERT REGISTERS (5XX)..........................................................................................................................33
4.8 RECEIVE DMA REGISTERS (7XX)............................................................................................................33
4.9 TRANSMIT DMA REGISTERS (8XX).........................................................................................................34
4.10 FIFO REGISTERS (9XX) ...........................................................................................................................34
4.11 PCI CONFIGURATION REGISTERS FOR FUNCTION 0 (PIDSEL/AXX) ......................................................35
4.12 PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX).......................................................35
5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT............................... 36
5.1 MASTER RESET AND ID REGISTER DESCRIPTION ...................................................................................36
5.2 MASTER CONFIGURATION REGISTER DESCRIPTION................................................................................37
5.3 STATUS AND INTERRUPT .........................................................................................................................39
5.3.1 General Description of Operation ......................................................................................................39
5.3.2 Status and Interrupt Register Description...........................................................................................41
5.4 TEST REGISTER DESCRIPTION .................................................................................................................46
6. LAYER 1......................................................................................................................................... 47
6.1 GENERAL DESCRIPTION...........................................................................................................................47
6.2 PORT REGISTER DESCRIPTIONS ...............................................................................................................49
6.3 BERT.......................................................................................................................................................51
6.4 BERT REGISTER DESCRIPTION ...............................................................................................................52
7. HDLC .............................................................................................................................................. 59
7.1 GENERAL DESCRIPTION...........................................................................................................................59
7.2 HDLC OPERATION ..................................................................................................................................59
7.3 BIT-SYNCHRONOUS HDLC REGISTER DESCRIPTION ..............................................................................61
8. FIFO ................................................................................................................................................ 65
8.1 GENERAL DESCRIPTION AND EXAMPLE ..................................................................................................65
8.1.1 Receive High Watermark ....................................................................................................................67
8.1.2 Transmit Low Watermark....................................................................................................................67
8.2 FIFO REGISTER DESCRIPTION.................................................................................................................68
9. DMA ................................................................................................................................................ 74
9.1 INTRODUCTION ........................................................................................................................................74
9.2 RECEIVE SIDE ..........................................................................................................................................76
9.2.1 Overview .............................................................................................................................................76
9.2.2 Packet Descriptors..............................................................................................................................80
9.2.3 Free Queue..........................................................................................................................................82