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DS3131

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Figure 3-1. Signal Floorplan

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Y RC0 PCLK PAD30 PAD29 PAD26 PIDSEL PAD21 PAD18 PCBE2* PTRDY*

PDEV-

SEL*

PSERR* PAD15 PAD12 PAD10 PCBE0* PAD5 PAD2 TEST

PXB-

LAST*

W RD1 RD0 PRST* PGNT* PAD27 PCBE3* PAD22 PAD19 NC

P-

FRAME*

PSTOP* PPAR PAD14 PAD11 PAD8 PAD6 PAD3 PINT* PXDS* TC0 W

V RD3 RC2 RC1 PREQ* PAD28 PAD25 PAD23 PAD20 PAD16 PIRDY* PPERR* PCBE1* PAD13 PAD9 PAD7 PAD4 PAD0 PXAS* TD0 TD2 V

U RC5 RC4 RD2 VSS PAD31 VDD PAD24 VSS PAD17 VDD VDD VSS VSS NC VDD PAD1 VSS TD1 TC1 TC3 U

R RD8 RD7 RC6 VDD VDD TC5 TC6 TD6 R

T RC7 RD5 RD4 RC3 TC2 TD3 TC4 TD4 T

P RD9 RC9 RC8 RD6 TD5 TC7 TD7 TC8 P

N RC11 RD10 RC10 VSS VSS TD8 TC9 TD9 N

M RD12 RC12 RD11 VSS VSST VSST VSST VSST TC10 TD10 TC11 TD11 M

L RC14 RD13 RC13 VDD VSST VSST VSST VSST VDD TD12 TC12 TC13 L

K RD14 RD15 RC15 VDD VSST VSST VSST VSST VDD TD14 TC14 TD13 K

J RC16 RD16 RC17 RD17 VSST VSST VSST VSST VSS TC16 TD15 TC15 J

H RC18 RD18 RC19 VSS VSS TD17 TC17 TD16 H

G RD19 RC20 RD20 RC22 TC21 TD19 TD18 TC18 G

F RC21 RD21 RD22 VDD VDD TD21 TC20 TC19 F

E RC23 RD23 RC24 RD25 TD24 TC23 TC22 TD20 E

D RD24 RD26 RC26 VSS

LA14-

RD30

VDD LA7-RC34 VSS VSS VDD VDD

LD15-

TD35

VSS LD6-TC31 VDD JTDO VSS TC25 TD23 TD22 D

C RC25 RC27

LA19-

RC28

LA15-

RC30

LA11-

RC32

LA8-RD33 LA4-RD35 LA0-RD37 LMS-RD39 NC

LHLDA-

TC38

LIM-TC36

LD12-

TC34

LD9-TD32 LD5-TD30 LD2-TC29 JTDI TD26 TD25 TC24 C

BRD27

LA17-

RC29

LA16-

RD29

LA12-

RD31

LA9-RC33 LA5-RC35 LA2-RD36 LCS-RC38 LBPXS

LHOLD-

TD39

LBHE-

TD37

LCLK-

TD36

LD13-

TD34

LD10-

TC33

LD7-TD31 LD3-TD29 JTRST JTCLK TC27 TC26 B

A VSS

LA18-

RD28

LA13-

RC31

LA10-

RD32

LA6-RD34 LA3-RC36 LA1-RC37 LRD-RD38

LWR-

RC39

LRDY-

TC39

LBGAC-

TD38

LINT-

TC37

LD14-

TC35

LD11-

TD33

LD8-TC32 LD4-TC30 LD1-TD28 LD0-TC28 JTMS TD27 A

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Receive Ports 0-13 Transmit Ports 0-13 PCI other VDD

Receive Ports 14-27 Transmit Ports 14-27 JTAG, TEST, and NC VSS

Local Bus and Ports 28-39 PCI address and data