Owner's manual

DS3131
154 of 174
Figure 11-12. 8-Bit Write Cycle
Motorola Mode (LIM = 1)
Arbitration Disabled (LARBE = 0)
Bus Transaction Time = Timed from LRDY
LRDYLRDY
LRDY (LRDY = 0000)
LCL
K
LA[19:0]
LD[7:0]
LD[15:8]
LR/
W
L
D
S
A
ddress Valid
L
BH
E
L
RD
Y
Three-State
Data Valid
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Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status
bit is set.