Owner's manual

DS3131
151 of 174
Figure 11-9. 8-Bit Read Cycle
Motorola Mode (LIM = 1)
Arbitration Enabled (LARBE = 1)
Bus Transaction Time = 6 LCLK (LRDY = 0110)
An attempted access by the host causes the local bus to request the bus. If bus access has not been granted
(LBGACK deasserted), the timing shown at the top of the page applies, with LBR being asserted. Once LBG is
detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has already been
granted (LBGACK asserted), the timing shown at the bottom of the page applies.
LCLK
L
B
R
L
B
G
L
BGAC
K
32 to 1,048,576 LCLKs
LA[19:0]
LD[7:0]
LD[15:8]
LR
/W
L
D
S
A
ddress Valid
Data Valid
L
BH
E
Three-State
Three-State
Three-State
Three-State
LCLK
123456
Note: LA, LD, LBH
E
, LD
S
, and LR
/
W are three-stated.