Owner's manual

DS3131
150 of 174
Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle
Intel Mode (LIM = 0)
Arbitration Disabled (LARBE = 0)
Bus Transaction Time = Timed from LRDY
LRDYLRDY
LRDY (LRDY = 0000)
LCLK
LA[19:0]
LD[7:0]
LD[15:8]
L
W
R
L
R
D
A
ddress Valid
L
BH
E
L
RD
Y
Data Valid
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Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the
LBE status bit is set.