Owner's manual

DS3131
148 of 174
Figure 11-6. 16-Bit Write Cycle
Intel Mode (LIM = 0)
Arbitration Enabled (LARBE = 1)
Bus Transaction Time = 4 LCLK (LRDY = 0100)
An attempted access by the host causes the local bus to request the bus. If bus access has not been granted
(LBGACK deasserted), the timing shown at the top of the page applies, with LHOLD being asserted. Once
LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has
already been granted (LBGACK asserted), the timing shown at the bottom of the page applies.
LCLK
LHOLD
LHLDA
L
BGAC
K
32 to 1,048,576 LCLKs
LA[19:0]
LD[7:0]
LD[15:8]
L
R
D
L
W
R
A
ddress Valid
L
BH
E
Data Valid
Data Valid
Three-State
Three-State
Three-State
Three-State
Three-State
Three-State
LCLK
1234
Note: LA, LD, LBH
E
, LW
R
, and LRD are three-stated.