Owner's manual

DS3131
10 of 174
Figure 2-1. Block Diagram
RC2
RD2
TC2
TD2
JTDO
PCL
K
PAD[31:0]
P
RS
T
P
CBE[3:0]
PPAR
P
FRAM
E
P
IRD
Y
P
TRD
Y
P
STO
P
P
IDSE
L
P
DEVSE
L
P
RE
Q
P
GN
T
P
PER
R
P
SER
R
RC39
RD39
TC39
TD39
RC0
RD0
TC0
TD0
RC1
RD1
TC1
TD1
P
XA
S
P
XD
S
P
XBLAS
T
J
TRS
T
JTDI
JTMS
JTCL
K
LA[19:0]
LD[15:0]
L
W
R
(LR/W)
L
RD(LDS)
LIM
L
IN
T
L
RD
Y
LMS
L
C
S
LHOLD(LB
R
)
LHLDA(LB
G
)
L
BGAC
K
LCL
K
PIN NAMES IN ( )
A
RE ACTIVE WHEN
THE DEVICE IS IN
THE MOT MODE
(i.e., LIM = 1).
L
BH
E
JTAG
TEST
ACCESS
(SECT. 12)
LOCAL BUS BLOC
K
(SECT. 11)
LAYER 1 BLOCK (SECT. 6)
40-BIT SYNCHRONOUS HDLC
CONTROLLERS (SECT. 7)
FIFO BLOCK (SECT. 8)
DMA BLOCK (SECT. 9)
PCI BLOCK (SECT. 10)
BERT
(SECT. 6)
RECEIVE DIRECTION
TRANSMIT DIRECTION
INTERNAL CONTROL BUS
LBPXS
DS3131