Manual

DS31256
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The host reads from the transmit done queue to find which data buffers and their associated descriptors
have completed transmission. The transmit done queue is circular. A set of internal addresses within the
device that are accessed by both the host and the DMA keep track of the circular queue addresses in the
transmit done queue. On initialization, the host configures all of the registers, as shown in Table 9-K.
After initialization, the DMA only writes to (changes) the write pointer and the host only writes to the
read pointer.
Empty Case
The transmit done queue is considered empty when the read and write pointers are identical.
Transmit Done-Queue Empty State
empty descriptor
empty descriptor
empty descriptor
read pointer > empty descriptor < write pointer
empty descriptor
empty descriptor
empty descriptor
Full Case
The transmit done queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Therefore, one descriptor must always remain empty.
Transmit Done-Queue Full State
valid descriptor
valid descriptor
empty descriptor < write pointer
read pointer > valid descriptor
valid descriptor
valid descriptor
valid descriptor
Table 9-K. Transmit Done-Queue Internal Address Storage
REGISTER NAME ADDRESS
Transmit Done-Queue Base Address 0 (lower word) TDQBA0 0830h
Transmit Done-Queue Base Address 1 (upper word) TDQBA1 0834h
Transmit Done-Queue DMA Write Pointer TDQWP 0840h
Transmit Done-Queue Host Read Pointer TDQRP 083Ch
Transmit Done-Queue End Address TDQEA 0838h
Transmit Done-Queue FIFO Flush Timer TDQFFT 0844h
Note: Transmit done-queue end address is not an absolute address. The absolute end address is “Base + TDQEA x 4.”