Manual

DS26519 16-Port T1/E1/J1 Transceiver
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Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0
0
A
13
LSB MSB
SPI_SCLK
C
S
B
SPI_MOSI
SPI_MISO
D7 D6 D5 D4 D3 D2 D1 D0
LSBMSB
A
4
A
3
A
2
A
1
A
0
LSBMSB
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
B
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0
SPI_SCLK
C
S
B
0
A
13
LSB MSB
SPI_MOSI
SPI_MISO
D7 D6 D5 D4 D3 D2 D1 D0
LSBMSB
A
4
A
3
A
2
A
1
A
0
LSBMSB
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
B
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1
SPI_SCL
K
C
S
B
0
A
13
LSB MSB
SPI_MOSI
SPI_MISO
D7 D6 D5 D4 D3 D2 D1 D0
LSBMSB
A
4
A
3
A
2
A
1
A
0
LSBMSB
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
B
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1
SPI_SCLK
C
S
B
0
A
13
LSB MSB
SPI_MOSI
SPI_MISO
D7 D6 D5 D4 D3 D2 D1 D0
LSBMSB
A
4
A
3
A
2
A
1
A
0
LSBMSB
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
B
9.2 Clock Structure
The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1
and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy.
9.2.1 Backplane Clock Generation
The DS26519 provides facility for provision of BPCLK[2:1] at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see
Figure 9-9). The Global Transceiver Clock Control Register 1 (GTCCR1) is used to control the backplane clock