Manual

DS26519 16-Port T1/E1/J1 Transceiver
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9.9.7 Maintenance and Alarms ..................................................................................................................... 72
9.9.8 Alarms .................................................................................................................................................. 75
9.9.9 Error Count Registers .......................................................................................................................... 77
9.9.10 DS0 Monitoring Function...................................................................................................................... 79
9.9.11 Transmit Per-Channel Idle Code Generation ...................................................................................... 80
9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 80
9.9.13 Per-Channel Loopback ........................................................................................................................ 80
9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)................................................................... 80
9.9.15 T1 Programmable In-Band Loop Code Generator............................................................................... 81
9.9.16 T1 Programmable In-Band Loop Code Detection................................................................................ 82
9.9.17 Framer Payload Loopbacks ................................................................................................................. 83
9.10 HDLC CONTROLLERS ................................................................................................................84
9.10.1 Receive HDLC Controller..................................................................................................................... 84
9.10.2 Transmit HDLC Controller.................................................................................................................... 87
9.11 POWER-SUPPLY DECOUPLING....................................................................................................89
9.12 LINE INTERFACE UNITS (LIUS)....................................................................................................90
9.12.1 LIU Operation....................................................................................................................................... 92
9.12.2 Transmitter........................................................................................................................................... 93
9.12.3 Receiver ............................................................................................................................................... 97
9.12.4 Hitless Protection Switching (HPS).................................................................................................... 101
9.12.5 Jitter Attenuator.................................................................................................................................. 102
9.12.6 LIU Loopbacks ................................................................................................................................... 103
9.13 BIT ERROR-RATE TEST FUNCTION (BERT)...............................................................................106
9.13.1 BERT Repetitive Pattern Set ............................................................................................................. 107
9.13.2 BERT Error Counter........................................................................................................................... 107
10. DEVICE REGISTERS.....................................................................................................108
10.1 REGISTER LISTINGS .................................................................................................................108
10.1.1 Global Register List............................................................................................................................ 109
10.1.2 Framer Register List........................................................................................................................... 110
10.1.3 LIU and BERT Register List............................................................................................................... 117
10.2 REGISTER BIT MAPS ................................................................................................................118
10.2.1 Global Register Bit Map..................................................................................................................... 118
10.2.2 Framer Register Bit Map.................................................................................................................... 119
10.2.3 LIU Register Bit Map.......................................................................................................................... 128
10.2.4 BERT Register Bit Map...................................................................................................................... 129
10.3 GLOBAL REGISTER DEFINITIONS...............................................................................................130
10.4 FRAMER REGISTER DESCRIPTIONS...........................................................................................156
10.4.1 Receive Register Descriptions........................................................................................................... 156
10.4.2 Transmit Register Descriptions.......................................................................................................... 214
10.5 LIU REGISTER DEFINITIONS .....................................................................................................250
10.6 BERT REGISTER DEFINITIONS .................................................................................................260
11. FUNCTIONAL TIMING ...................................................................................................268
11.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................268
11.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................273
11.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................278
11.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................282
12. OPERATING PARAMETERS.........................................................................................287
12.1 THERMAL CHARACTERISTICS....................................................................................................288
12.2 LINE INTERFACE CHARACTERISTICS..........................................................................................288
13. AC TIMING CHARACTERISTICS ..................................................................................289
13.1 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................289
13.1.1 SPI Bus Mode .................................................................................................................................... 289
13.2 JTAG INTERFACE TIMING.........................................................................................................300