Manual
DS26519 16-Port T1/E1/J1 Transceiver
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10.3 Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, IBO configuration, MCLK configuration, and BPCLKn configuration. The global registers bit
descriptions are presented below.
Note: Each global register controls eight of the 16 ports, either Ports 1–8 or 9–16.
Table 10-11. Global Register Set
ADDRESS NAME DESCRIPTION R/W
CHANNELS 1–8
00F0h GTCR1 Global Transceiver Control Register 1 R/W
00F1h GFCR1 Global Framer Control Register 1 R/W
00F2h GTCR3 Global Transceiver Control Register 3 R/W
00F3h GTCCR1 Global Transceiver Clock Control Register 1 R/W
00F4h GTCCR3 Global Transceiver Clock Control Register 3 R/W
00F5h — Reserved. —
00F6h GSRR1 Global LIU Software Reset Register 1 R/W
00F7h — Reserved. —
00F8h IDR Device Identification Register R
00F9h GFISR1 Global Framer Interrupt Status Register 1 R
00FAh GBISR1 Global BERT Interrupt Status Register 1 R
00FBh GLISR1 Global LIU Interrupt Status Register 1 R
00FCh GFIMR1 Global Framer Interrupt Mask Register 1 RW
00FDh GBIMR1 Global BERT Interrupt Mask Register 1 R/W
00FEh GLIMR1 Global LIU Interrupt Mask Register 1 R/W
00FFh GPIORR1 General-Purpose I/O Read Register 1 R/W
CHANNELS 9–16
20F0h GTCR2 Global Transceiver Control Register 2 R/W
20F1h GFCR2 Global Framer Control Register 2 R/W
20F2h GTCR4 Global Transceiver Control Register 4 R/W
20F3h GTCCR2 Global Transceiver Clock Control Register 2 R/W
20F4h GTCCR4 Global Transceiver Clock Control Register 4 R/W
20F5h — Reserved. —
20F6h GSRR2 Global LIU Software Reset Register 2 R/W
20F7h — Reserved. —
20F8h — Reserved. —
20F9h GFISR2 Global Framer Interrupt Status Register 2 R
20FAh GBISR2 Global BERT Interrupt Status Register 2 R
20FBh GLISR2 Global LIU Interrupt Status Register 2 R
20FCh GFIMR2 Global Framer Interrupt Mask Register 2 R/W
20FDh GBIMR2 Global BERT Interrupt Mask Register 2 R/W
20FEh GLIMR2 Global LIU Interrupt Mask Register 2 R/W
20FFh GPIORR2 General-Purpose I/O Read Register 2 R/W
Note 1: Reserved registers should only be written with all zeros.
Note 2: The global registers are located in the framer 1 and 9 address space. The corresponding address space for the other 14 framers
is “Reserved,” and should be initialized with all zeros for proper operation.