Instruction Manual

DS26503 T1/E1/J1 BITS Element
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7.3 Register Map
Table 7-2. Register Map Sorted By Address
ADDRESS TYPE REGISTER NAME
REGISTER
ABBREVIATION
00 R/W Test Reset Register TSTRREG
01 R/W I/O Configuration Register 1 IOCR1
02 R/W I/O Configuration Register 2 IOCR2
03 R/W T1 Receive Control Register 1 T1RCR1
04 R/W T1 Receive Control Register 2 T1RCR2
05 R/W T1 Transmit Control Register 1 T1TCR1
06 R/W T1 Transmit Control Register 2 T1TCR2
07 R/W T1 Common Control Register T1CCR
08 R/W Mode Configuration Register MCREG
09 R/W Transmit PLL Control Register TPCR
0A — Reserved —
0B — Reserved —
0C — Reserved —
0D — Reserved —
0E — Reserved —
0F — Reserved —
10 R Device Identification Register IDR
11 R Information Register 1 INFO1
12 R Information Register 2 INFO2
13 R Interrupt Information Register IIR
14 R Status Register 1 SR1
15 R/W Interrupt Mask Register 1 IMR1
16 R Status Register 2 SR2
17 R/W Interrupt Mask Register 2 IMR2
18 R Status Register 3 SR3
19 R/W Interrupt Mask Register 3 IMR3
1A R Status Register 4 SR4
1B R/W Interrupt Mask Register 4 IMR4
1C R Information Register 3 INFO3
1D R/W E1 Receive Control Register E1RCR
1E R/W E1 Transmit Control Register E1TCR
1F R/W BOC Control Register BOCC
20 R/W Loopback Control Register LBCR
21-2F — Reserved —
30 R/W Line Interface Control 1 LIC1
31 R/W Line Interface Control 2 LIC2
32 R/W Line Interface Control 3 LIC3
33 R/W Line Interface Control 4 LIC4
34 R/W Transmit Line Build-Out Control TLBC
35-3F — Reserved —
40 R/W Transmit Align Frame Register TAF
41 R/W Transmit Non-Align Frame Register TNAF
42 R/W Transmit Si Align Frame TSiAF