Owner's manual

DS26502 T1/E1/J1/64KCC BITS Element
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7.7 INTERRUPT INFORMATION REGISTERS..............................................................................39
8. T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40
8.1 T1 CONTROL REGISTERS ...............................................................................................40
9. E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46
9.1 E1 CONTROL REGISTERS ...............................................................................................46
9.2 E1 INFORMATION REGISTERS..........................................................................................48
10. I/O PIN CONFIGURATION OPTIONS ............................................................................52
11. T1 SYNCHRONIZATION STATUS MESSAGE ..............................................................55
11.1 T1 BIT-ORIENTED CODE (BOC) CONTROLLER ................................................................55
11.2 TRANSMIT BOC.............................................................................................................55
11.3 RECEIVE BOC...............................................................................................................56
12. E1 SYNCHRONIZATION STATUS MESSAGE..............................................................64
12.1 SA/SI BIT ACCESS BASED ON CRC4 MULTIFRAME...........................................................64
12.2 ALTERNATE SA/SI BIT ACCESS BASED ON DOUBLE-FRAME...............................................74
13. LINE INTERFACE UNIT (LIU) ........................................................................................77
13.1 LIU OPERATION ............................................................................................................78
13.2 LIU RECEIVER ..............................................................................................................78
13.2.1 Receive Level Indicator............................................................................................78
13.2.2 Receive G.703 Section 10 Synchronization Signal ..................................................79
13.2.3 Monitor Mode ...........................................................................................................79
13.3 LIU TRANSMITTER .........................................................................................................79
13.3.1 Transmit Short-Circuit Detector/Limiter ....................................................................80
13.3.2 Transmit Open-Circuit Detector................................................................................80
13.3.3 Transmit BPV Error Insertion ...................................................................................80
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)................................80
13.4 MCLK PRE-SCALER......................................................................................................80
13.5 J
ITTER ATTENUATOR......................................................................................................80
13.6 CMI (CODE MARK INVERSION) OPTION...........................................................................81
13.7 LIU C
ONTROL REGISTERS .............................................................................................82
13.8 RECOMMENDED CIRCUITS ..............................................................................................90
13.9 C
OMPONENT SPECIFICATIONS ........................................................................................92
14. LOOPBACK CONFIGURATION.....................................................................................96
15. 64KHZ SYNCHRONIZATION INTERFACE....................................................................97
15.1 R
ECEIVE 64KHZ SYNCHRONIZATION INTERFACE OPERATION ............................................97
15.2 TRANSMIT 64KHZ SYNCHRONIZATION INTERFACE OPERATION ..........................................98
16. 6312KHZ SYNCHRONIZATION INTERFACE................................................................99
16.1 R
ECEIVE 6312KHZ SYNCHRONIZATION INTERFACE OPERATION ........................................99
16.2 T
RANSMIT 6312KHZ SYNCHRONIZATION INTERFACE OPERATION.......................................99
17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................100
17.1 I
NSTRUCTION REGISTER...............................................................................................104