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REV: 070904

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

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GENERAL DESCRIPTION

The DS26502 is a building-integrated timing-

supply (BITS) clock-recovery element. The

receiver portion can recover a clock from T1,

E1, 64kHz composite clock, and 6312kHz

synchronization timing interfaces. In T1 and E1

modes, the Synchronization Status Message

(SSM) can also be recovered. The transmit

portion can directly interface to T1, E1, or

64kHz composite clock synchronization

interfaces as well as source the SSM in T1 and

E1 modes. The DS26502 can translate between

any of the supported inbound synchronization

clock rates to any supported outbound rate. A

separate output is provided to source a 6312kHz

clock. The device is controlled through a

parallel, serial, or hardware controller port.

APPLICATIONS

BITS Timing

Rate Conversion

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS26502L 0°C to +70°C 64 LQFP

DS26502LN -40°C to +85°C 64 LQFP

FEATURES

§ G.703 2048kHz Synchronization Interface

Compliant

§ G.703 64kHz Centralized (Option A) and

Codirectional Timing Interface Compliant

§ G.703 Appendix II 64kHz and 6312kHz

Japanese Synchronization Interface

Compliant

§ Interfaces to Standard T1/J1 (1.544MHz) and

E1 (2.048MHz)

§ Interface to CMI-Coded T1/J1 and E1

§ Short- and Long-Haul Line Interface

§ Transmit and Receive T1 and E1 SSM

Messages with Message Validation

§ Crystal-Less Jitter Attenuator with Bypass

Mode

§ Fully Independent Transmit and Receive

Functionality

§ Internal Software-Selectable Receive- and

Transmit-Side Termination for

75Ω/100Ω/110Ω/120Ω T1, E1, and

Composite Clock Interfaces

§ Monitor Mode for Bridging Applications

§ Accepts 16.384MHz, 8.192MHz, 4.096MHz,

or 2.048MHz Master Clock

§ 64kHz, 8kHZ, and 400Hz Outputs in

Composite Clock Mode

§ 8-Bit Parallel Control Port, Multiplexed or

Nonmultiplexed, Intel or Motorola

§ Serial (SPI) Control Port

§ Hardware Control Mode

§ Provides LOS, AIS, and LOF Indications

Through Hardware Output Pins

§ Fast Transmitter-Output Disable Through

Device Pin for Protection Switching

§ IEEE 1149.1 JTAG Boundary Scan

§ 3.3V Supply with 5V-Tolerant Inputs and

Outputs

DS26502

T1/E1/J1/64KCC BITS Element

www.maxim-ic.com

Summary of content (125 pages)

PAGE 1
DS26502 T1/E1/J1/64KCC BITS Element www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26502 is a building-integrated timingsupply (BITS) clock-recovery element. The receiver portion can recover a clock from T1, E1, 64kHz composite clock, and 6312kHz synchronization timing interfaces. In T1 and E1 modes, the Synchronization Status Message (SSM) can also be recovered.
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DS26502 T1/E1/J1/64KCC BITS Element TABLE OF CONTENTS 1. FEATURES .......................................................................................................................7 1.1 1.2 1.3 1.4 1.5 1.6 GENERAL ........................................................................................................................7 LINE INTERFACE ...............................................................................................................7 JITTER ATTENUATOR ......................
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DS26502 T1/E1/J1/64KCC BITS Element 7.7 8. INTERRUPT INFORMATION REGISTERS ..............................................................................39 T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40 8.1 9. T1 CONTROL REGISTERS ...............................................................................................40 E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46 9.1 9.2 E1 CONTROL REGISTERS ..........
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DS26502 T1/E1/J1/64KCC BITS Element 17.2 17.3 17.4 17.5 18. TEST REGISTERS .........................................................................................................105 BOUNDARY SCAN REGISTER.........................................................................................105 BYPASS REGISTER ......................................................................................................105 IDENTIFICATION REGISTER..................................................................
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DS26502 T1/E1/J1/64KCC BITS Element LIST OF FIGURES Figure 3-1. Block Diagram ..................................................................................................................... 12 Figure 3-2. Loopback Mux Diagram....................................................................................................... 13 Figure 3-3. Transmit PLL Clock Mux Diagram ....................................................................................... 13 Figure 3-4. Master Clock PLL Diagram...
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DS26502 T1/E1/J1/64KCC BITS Element LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications...................................................................... 9 Table 2-2. E1-Related Telecommunications Specifications ................................................................... 10 Table 5-1. LQFP Pinout......................................................................................................................... 23 Table 6-1. Transmit Clock Source .........................
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DS26502 T1/E1/J1/64KCC BITS Element 1. FEATURES 1.1 General § § § § § 64-pin, 10mm x 10mm LQFP package 3.3V supply with 5V-tolerant inputs and outputs Evaluation kits IEEE 1149.1 JTAG Boundary Scan Driver source code available from the factory 1.2 Line Interface § § § § § § § § § § § § § § § § § § § Requires a single master clock (MCLK) for E1, T1, or J1 operation. Master clock can be 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz, 6.176MHz, or 12.
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DS26502 T1/E1/J1/64KCC BITS Element 1.4 Framer/Formatter § § § § § § Full receive and transmit path transparency T1 framing formats include D4 and ESF E1 framing formats include FAS and CRC4 Detailed alarm and status reporting with optional interrupt support RLOF, RLOS, and RAIS alarms interrupt on change of state Japanese J1 support includes: - Ability to calculate and check CRC6 according to the Japanese standard - Ability to generate yellow alarm according to the Japanese standard 1.
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DS26502 T1/E1/J1/64KCC BITS Element 2. SPECIFICATIONS COMPLIANCE The DS26502 meets all applicable sections of the relevant latest telecommunications specifications. The following table provides the T1 and E1 specifications and relevant sections that are applicable to the DS26502. Table 2-1. T1-Related Telecommunications Specifications ANSI T1.102- Digital Hierarchy Electrical Interface AMI Coding B8ZS Substitution Definition DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.4V to 3.
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DS26502 T1/E1/J1/64KCC BITS Element Table 2-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75W coax or 120W twisted pair; peak-to-peak space voltage is ±0.237V; nominal pulse width is 244ns. Return loss 51Hz to 102Hz is 6dB; 102Hz to 3072Hz is 8dB; 2048Hz to 3072Hz is 14dB. Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
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DS26502 T1/E1/J1/64KCC BITS Element Table 2-3.
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DS26502 T1/E1/J1/64KCC BITS Element 3. BLOCK DIAGRAMS Figure 3-1.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 3-2. Loopback Mux Diagram CLOCK FROM RX LIU RCLK JITTER ATTENUATOR ENABLED AND IN RX PATH + DATA TO RX FRAMER + DATA - DATA - DATA LOCAL LOOPBACK (LBCR.3) TX CLOCK CLOCK TO TX LIU JITTER ATTENUATOR ENABLED AND IN TX PATH + DATA + DATA FROM TX FORMATTER - DATA - DATA REMOTE LOOPBACK (LBCR.4) Figure 3-3. Transmit PLL Clock Mux Diagram TPCR.3 TPCR.4 TPCR.6 TPCR.7 IN SEL OUT SEL TPCR.5 TPCR.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 3-4. Master Clock PLL Diagram MCLK PIN PRE-SCALER DIVIDE BY 1, 2, 4, OR 8 X12,X16 MULTIPLIER PLL LIC4.6 (MPS0) LIC4.7 (MPS1) JA CLOCK 2.048MHz to 1.544MHz PLL TO CLOCK AND DATA RECOVERY ENGINE IN RECEIVE LIU LIC2.
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DS26502 T1/E1/J1/64KCC BITS Element 4. PIN FUNCTION DESCRIPTION 4.1 Transmit PLL NAME TYPE PLL_OUT O TCLK I FUNCTION Transmit PLL Output. 1544kHz, 2048kHz, 64kHz, or 6312kHz output from the internal TX PLL. Transmit Clock Input. A 64kHz, 1.544MHz, 2.048MHz, or 6312kHz primary clock. May be selected by the TX PLL mux to provide a clock to the transmit section. 4.2 Transmit Side NAME TYPE TSER I TS_8K_4 I/O TCLKO O TPOSO O TNEGO O FUNCTION Transmit Serial Data.
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DS26502 T1/E1/J1/64KCC BITS Element 4.3 Receive Side NAME TYPE RCLK O RS_8K O 400HZ O RSER O RLOF_CCE O RLOS O RAIS O FUNCTION Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), 6312 kHz (G.703 Synchronization Interface), or 64 kHz (Composite Clock) clock. Receive Sync/ 8kHZ Clock. T1/E1 Mode: An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries. If set to output frame boundaries, then through IOCR1.
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DS26502 T1/E1/J1/64KCC BITS Element 4.4 Controller Interface NAME TYPE INT/ JACKS I/O TMODE1 I TMODE2 I TSTRST I BIS[1:0] I AD[7]/ RITD I/O AD[6]/ TITD I/O AD[5]/ RMODE1 I/O FUNCTION Interrupt/JA Clock Source Select 1 INT: Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output. JACKS: Hardware Mode: JA Clock Select. Set this pin high for T1 mode operation when either a 2.048MHz, 4.096MHz, 8.192MHz or 16.
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DS26502 T1/E1/J1/64KCC BITS Element NAME TYPE AD[4]/ RMODE0 I/O AD[3]/TSM I/O AD[2]/RSM/ SCLK I/O AD[1]/ RMODE3/ MOSI I/O AD[0]/ TCSS0/ MISO I/O TCSS1 I FUNCTION Data Bus D[4] or Address/Data Bus AD[4]/Receive Framing Mode Select Bit 0 A[4]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus D[4]. AD[4]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the multiplexed address/data bus AD[4].
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DS26502 T1/E1/J1/64KCC BITS Element NAME TYPE A6/MPS0 I A5/CPOL/ TMODE0 I A4/CPHA/ L2 I A3/L1 I A2/L0 I A1/TAIS I FUNCTION Address Bus Bit A[6]/MCLK Prescale Select A6: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[6]. In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and should be tied low. MPS0: In Hardware Mode (BIS[1:0] = 11), MCLK prescale select is used to set the prescale value for the PLL.
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DS26502 T1/E1/J1/64KCC BITS Element NAME TYPE A0/E1TS I BTS/HBE I RD(DS)/ RMODE2 I CS/RLB I ALE (AS)/ A7/MPS1 I WR (R/W)/ TMODE3 I FUNCTION Address Bus Bit A[0]/E1 Termination Select A0: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[0]. In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and should be tied low. E1TS: In Hardware Mode (BIS[1:0] = 11), selects the E1 internal termination value (0 = 120W, 1 = 75W).
PAGE 21
DS26502 T1/E1/J1/64KCC BITS Element 4.5 JTAG NAME TYPE JTCLK I JTMS I JTDI I JTDO O JTRST I FUNCTION JTAG Clock. This clock input is typically a low frequency (less than 10MHz) 50% duty cycle clock signal. JTAG Mode Select (with Pullup). This input signal is used to control the JTAG controller state machine and is sampled on the rising edge of JTCLK. JTAG Data Input (with Pullup).
PAGE 22
DS26502 T1/E1/J1/64KCC BITS Element 4.7 Power NAME TYPE DVDD — RVDD — TVDD — DVSS — RVSS — TVSS — FUNCTION Digital Positive Supply. 3.3V ±5%. Should be tied to the RVDD and TVDD pins. Receive Analog Positive Supply. 3.3V ±5%. Should be tied to the DVDD and TVDD pins. Transmit Analog Positive Supply. 3.3V ±5%. Should be tied to the DVDD and RVDD pins. Digital Signal Ground. 0.0V. Should be tied to the RVSS and TVSS pins. Receive Analog Signal Ground. 0.0V.
PAGE 23
DS26502 T1/E1/J1/64KCC BITS Element 5. PINOUT Table 5-1.
PAGE 24
DS26502 T1/E1/J1/64KCC BITS Element I O O O I PARALLEL PORT TCLK TCLKO TNEGO TPOSO TSER MODE SERIAL PORT TCLK TCLKO TNEGO TPOSO TSER 23 I/O TS_8K_4 TS_8K_4 TS_8K_4 25 O RCLK RCLK RCLK 26 O RS_8K RS_8K RS_8K 27 28 29 30 O O O O 400HZ RSER RAIS RLOF_CCE 400HZ RSER RAIS RLOF_CCE 400HZ RSER RAIS RLOF_CCE 31 I — — TCSS1 32 33 34 35 36 37 38 39 40, 43, 45 41 42 44 O I I I I O I I RLOS JTMS JTCLK JTRST JTDI JTDO RVDD TSTRST RLOS JTMS JTCLK JTRST JTDI JTDO RVDD TSTRST RLOS JTMS JTCL
PAGE 25
DS26502 T1/E1/J1/64KCC BITS Element I I PARALLEL PORT BIS0 BIS1 MODE SERIAL PORT BIS0 BIS1 60 I CS CS RLB 61 I RD (DS) — RMODE2 62 I WR (R/W) — TMODE3 63 I/O AD0 MIS0 TCSS0 64 I/O AD1 MOSI RMODE3 PIN TYPE 57 59 HARDWARE BIS0 BIS1 25 of 125 FUNCTION Bus Interface Select Mode 0 Bus Interface Select Mode 1 Parallel Port Mode: Chip Select (Active Low) Serial Port Mode: Chip Select (Active Low) Hardware Mode: Remote Loopback Enable Parallel Port Mode: Read Input (Data Strobe), A
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DS26502 T1/E1/J1/64KCC BITS Element 6. HARDWARE CONTROLLER INTERFACE In Hardware Controller mode, the parallel and serial port pins are reconfigured to provide direct access to certain functions in the port. Only a subset of the device’s functionality is available in hardware mode. Each register description throughout the data sheet indicates the functions that may be controlled in hardware mode and several alarm indicators that are available in both hardware and processor mode.
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DS26502 T1/E1/J1/64KCC BITS Element 6.3 Line Build-Out Table 6-3. E1 Line Build-Out L2 PIN 13 0 0 1 1 1 1 L1 PIN 12 0 0 0 0 1 1 L0 PIN 11 0 1 0 1 0 1 APPLICATION N (1) RETURN LOSS Rt (1) 75Ω normal 120Ω normal 75Ω with high return loss* 120Ω with high return loss* Reserved Reserved 1:2 1:2 1:2 1:2 — — N.M. N.M. 21dB 21dB — — 0 0 6.2Ω 11.6Ω — — *TTD pin must be connected high in this mode. N.M. = not meaningful Table 6-4.
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DS26502 T1/E1/J1/64KCC BITS Element 6.5 Transmitter Operating Modes Table 6-6.Transmit Path Operating Mode TMODE3 PIN 62 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 1: Note 2: TMODE2 PIN 48 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 TMODE1 PIN 49 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 TMODE0 PIN 14 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 TRANSMIT PATH OPERATING MODE T1 D4 T1 ESF J1 D4 J1 ESF E1 FAS E1 FAS + CAS (Note 1) Reserved E1 CRC4 E1 CRC4 + CAS (Note 1) Reserved E1 G.
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DS26502 T1/E1/J1/64KCC BITS Element Table 6-8. MCLK Pre-Scaler for E1 Mode MPS1 PIN 16 0 0 0 0 1 1 1 1 MPS0 PIN 15 0 0 1 1 0 0 1 1 JACKS PIN 46 0 1 0 1 0 1 0 1 MCLK (MHz) 2.048 Reserved 4.096 Reserved 8.192 Reserved 16.384 Reserved 6.7 Other Hardware Controller Mode Features Table 6-9. Other Operational Modes PIN NAME RSM PIN 1 TSM PIN2 RLB PIN 60 TAIS PIN 10 HBE PIN 55 DESCRIPTION RS_8K Mode Select: Selects frame or multiframe pulse at RS_8K pin.
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DS26502 T1/E1/J1/64KCC BITS Element 7. PROCESSOR INTERFACE The DS26502 is controlled via a nonmultiplexed (BIS[1:0] = 01) or a multiplexed (BIS[1:0] = 00) parallel bus. There is also a serial bus mode option, as well as a hardware mode of operation. The bus interface type is selected by BIS1 and BIS0 as shown in Table 7-1. Table 7-1. Port Mode Select BIS1 0 0 1 1 BIS0 0 1 0 1 PORT MODE Parallel Port Mode (Multiplexed) Parallel Port Mode (Nonmultiplexed) Serial Port Mode (SPI) Hardware Mode 7.
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DS26502 T1/E1/J1/64KCC BITS Element are terminated when CS is removed. If CS is removed before all 8 bits of the data are read, the remaining data will be lost. If CS is removed before all 8 bits of data are written to the part, no write access will occur and the target register will not be updated. Note: During a Burst read access, data must be fetched internally to the part as the LSB of the previous byte is transmitted out.
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DS26502 T1/E1/J1/64KCC BITS Element 7.3 Register Map Table 7-2.
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DS26502 T1/E1/J1/64KCC BITS Element ADDRESS TYPE 43 44 45 46 47 48 49 4A 4B-4F 50 51 52 53 54-55 56 57 58 59 5A 5B 5C 5D 5E 5F 60-EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF R/W R/W R/W R/W R/W R/W R/W R/W — R R/W R/W R/W — R R R R R R R R R R — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REGISTER NAME Transmit Si Non-Align Frame Transmit Remote Alarm Bits Transmit Sa4 Bits Transmit Sa5 Bits Transmit Sa6 Bits Transmit Sa7 Bits Transmit Sa8 Bits Transmit Sa Bit Control Registe
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DS26502 T1/E1/J1/64KCC BITS Element 7.3.1 Power-Up Sequence The DS26502 contains an on-chip power-up reset function, which automatically clears the writeable register space immediately after power is supplied to the device. The user can issue a chip reset at any time. Issuing a reset will disrupt signals flowing through the DS26502 until the device is reprogrammed. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register.
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DS26502 T1/E1/J1/64KCC BITS Element 7.3.3 Mode Configuration Register Register Name: Register Description: Register Address: Bit # Name Default HW Mode 7 TMODE3 0 TMODE3 PIN 62 MCREG Mode Configuration Register 08h 6 TMODE2 0 TMODE2 PIN 48 5 TMODE1 0 TMODE1 PIN 49 4 TMODE0 0 TMODE0 PIN 14 3 RMODE3 0 RMODE3 PIN 64 2 RMODE2 0 RMODE2 PIN 61 1 RMODE1 0 RMODE1 PIN 4 0 RMODE0 0 RMODE0 PIN 3 Bit 0-3/Receive Mode Configuration (RMODE[3:0]).
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DS26502 T1/E1/J1/64KCC BITS Element Bit 4-7/ Transmit Mode Configuration (TMODE[3:0]). Used to select the operating mode of the transmit path for the DS26502. TMODE3 0 0 TMODE2 0 0 TMODE1 0 0 TMODE0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 Note 1: Note 2: Transmit Path Operating Mode T1 D4 T1 ESF (Note: In this mode the TFSE (T1TCR2.6) bit should be set = 0.
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DS26502 T1/E1/J1/64KCC BITS Element Bit 3-4/Transmit PLL Input Frequency Select (TPLLIFS[1:0]). These bits are used to indicate the reference frequency being input to the TX PLL. TPLLIFS1 TPLLIFS0 Input Frequency 0 0 1 1 0 1 0 1 1.544MHz 2.048MHz 64kHz 6312kHz Bit 5/ PLL_OUT Select (PLLOS). This bit selects the source for the PLL_OUT pin. See Figure 3-3. 0 = PLL_OUT is sourced directly from the TX PLL. 1 = PLL_OUT is the output of the TX PLL mux.
PAGE 38
DS26502 T1/E1/J1/64KCC BITS Element 7.4 Interrupt Handling Various alarms, conditions, and events in the DS26502 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts. Each status register has an associated interrupt mask register. For example, SR1 (Status Register 1) has an interrupt control register called IMR1 (Interrupt Mask Register 1).
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DS26502 T1/E1/J1/64KCC BITS Element 7.6 Information Registers Information registers operate the same as status registers except they cannot cause interrupts. INFO3 register is a read-only register and it reports the status of the E1 synchronizer in real time. INFO3 information bits are not latched, and it is not necessary to precede a read of these bits with a write. 7.
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DS26502 T1/E1/J1/64KCC BITS Element 8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26502 is configured via a set of five control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26502 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: T1RCR2 T1 Receive Control Register 2 04h Bit # Name Default HW Mode 7 — 0 6 — 0 0 0 5 RB8ZS 0 HBE PIN55 4 — 0 3 — 0 2 — 0 1 RJC 0 0 RD4YM 0 0 0 0 0 0 Bit 0/Receive Side D4 Yellow Alarm Select (RD4YM). 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode) Bit 1/Receive Japanese CRC6 Enable (RJC).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode 7 TJC 0 RMODEx PINS T1TCR1 T1 Transmit Control Register 1 05h 6 TFPT 0 5 TCPT 0 4 — 0 3 — 0 2 — 0 1 — 0 0 TYEL 0 0 0 0 0 0 0 0 Bit 0/Transmit Yellow Alarm (TYEL). 0 = do not transmit yellow alarm 1 = transmit yellow alarm Bit 1/Unused, must be set = 0 for proper operation. Bit 2/Unused, must be set = 0 for proper operation. Bit 3/Unused, must be set = 0 for proper operation.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode 7 TB8ZS 0 HBE PIN 55 T1TCR2 T1 Transmit Control Register 2 06h 6 TFSE 1 5 — 0 4 FBCT2 0 3 FBCT1 0 2 TD4YM 0 1 — 0 0 TB7ZS 0 1 0 0 0 0 0 0 Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS). 0 = no stuffing occurs 1 = bit 7 forced to a 1 in channels with all 0s Bit 1/Unused, must be set = 0 for proper operation. Bit 2/Transmit-Side D4 Yellow Alarm Select (TD4YM).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode T1CCR T1 Common Control Register 07h 7 — 0 6 — 0 5 — 0 4 TRAI-CI 0 3 TAIS-CI 0 2 — 0 1 PDE 0 0 — 0 0 0 0 0 0 0 0 0 Bit 0/Unused, must be set = 0 for proper operation. Bit 1/Pulse-Density Enforcer Enable (PDE). The framer always examines the transmit and receive data streams for violations of these, which are required by ANSI T1.
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DS26502 T1/E1/J1/64KCC BITS Element Table 8-1. T1 Alarm Criteria ALARM Blue Alarm (AIS) (Note 1) SET CRITERIA CLEAR CRITERIA Over a 3ms window, five or fewer zeros are received Over a 3ms window, six or more zeros are received Bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences Bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences Yellow Alarm (RAI) D4 Bit-2 Mode (T1RCR2.0 = 0) D4 12th F-bit Mode (T1RCR2.
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DS26502 T1/E1/J1/64KCC BITS Element 9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26502 is configured via a set of two control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26502 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There is one receive control register (E1RCR) and one transmit control register (E1TCR).
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DS26502 T1/E1/J1/64KCC BITS Element Table 9-1. E1 Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL FAS CRC4 SYNC CRITERIA RESYNC CRITERIA FAS present in frame N and N + 2, and FAS not present in frame N + 1 Three consecutive incorrect FAS received G.706 4.1.1 4.1.2 Alternate: (E1RCR.
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DS26502 T1/E1/J1/64KCC BITS Element 9.2 E1 Information Registers Register Name: Register Description: Register Address: INFO2 Information Register 2 12h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 — 0 3 — 0 2 CRCRC 0 1 FASRC 0 0 CASRC 0 X X X X X X X X Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error. Bit 1/FAS Resync Criteria Met Event (FASRC. Set when three consecutive FAS words are received in error.
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DS26502 T1/E1/J1/64KCC BITS Element Table 9-2. E1 Alarm Criteria ALARM SET CRITERIA RLOF An RLOF condition exists on power-up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated via E1RCR.0 255 or 2048 consecutive zeros received as determined by E1RCR.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode SR2 Status Register 2 16h 7 RYELC 0 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RYEL 0 X X X X X 2 RAIS 0 RAIS PIN 29 1 RLOS 0 RLOS PIN 32 0 RLOF 0 LOF PIN 30 Bit 0/Receive Loss of Frame Condition (RLOF). Set when the DS26502 is not synchronized to the received data stream. Bit 1/Receive Loss Of Signal Condition (RLOS). Set when 255 (or 2048 if E1RCR.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode IMR2 Interrupt Mask Register 2 17h 7 RYELC 0 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RYEL 0 2 RAIS 0 1 RLOS 0 0 RLOF 0 X X X X X X X X Bit 0/Receive Loss of Frame Condition (RLOF). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising edge only Bit 1/Receive Loss Of Signal Condition (RLOS).
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DS26502 T1/E1/J1/64KCC BITS Element 10. I/O PIN CONFIGURATION OPTIONS Register Name: Register Description: Register Address: IOCR1 I/O Configuration Register 1 01h Bit # Name Default HW Mode 7 — 0 6 RSMS2 0 0 0 5 RSMS1 0 RSM PIN 1 4 RLOFF 0 CSM_TSDW 3 0 0 0 2 TSM 0 TSM PIN 2 1 TSIO 0 0 ODF 0 0 0 Bit 0/Output Data Format (ODF). 0 = bipolar data at TPOS and TNEG 1 = NRZ data at TPOS; TNEG = 0 Bit 1/TS_8K_4 I/O Select (TSIO).
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DS26502 T1/E1/J1/64KCC BITS Element Table 10-1. TS_8K_4 Pin Functions TRANSMIT MODE T1/E1 T1/E1 T1/E1 T1/E1 64KCC 64KCC 64KCC 64KCC IOCR1.3 IOCR1.2 IOCR1.1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 TS_8K_4 FUNCTION Frame sync input Frame sync output Multiframe sync input Multiframe sync output 8kHz input reference 8kHz output reference 400Hz input reference 400Hz output reference Table 10-2. RLOF_CCE Pin Functions RECEIVE MODE T1/E1 T1/E1 64KCC IOCR1.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode IOCR2 I/O Configuration Register 2 02h 7 RCLKINV 6 TCLKINV 5 RS_8KINV 4 TS_8K_4INV 3 — 2 — 1 — 0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0/Unused, must be set = 0 for proper operation. Bit 1/Unused, must be set = 0 for proper operation. Bit 2/Unused, must be set = 0 for proper operation. Bit 3/Unused, must be set = 0 for proper operation.
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DS26502 T1/E1/J1/64KCC BITS Element 11. T1 SYNCHRONIZATION STATUS MESSAGE The DS26502 has a BOC controller to handle SSM services in T1 mode. Table 11-1.
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DS26502 T1/E1/J1/64KCC BITS Element 11.3 Receive BOC The receive BOC function is enabled by setting BOCC.4 = 1. The RFDL register will now operate as the receive BOC message and information register. The lower six bits of the RFDL register (BOC message bits) are preset to all ones. When the BOC bits change state, the BOC change of state indicator, SR3.0 will alert the host. The host will then read the RFDL register to get the BOC message.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: BOCC BOC Control Register 1Fh Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 RBOCE 0 3 RBR 0 2 RBF1 0 1 RBF0 0 0 SBOC 0 0 0 0 0 0 0 0 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TFDL register. Bits 1-2/Receive BOC Filter Bits (RBF0, RBF1).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: RFDL (RFDL register bit usage when BOCC.4 = 1) Receive FDL Register 50h Bit # Name Default HW Mode 7 — 0 6 — 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 0 0 0 0 0 0 0 0 Bit 0/BOC Bit 0 (RBOC0). Bit 1/BOC Bit 1 (RBOC1). Bit 2/BOC Bit 2 (RBOC2). Bit 3/BOC Bit 3 (RBOC3). Bit 4/BOC Bit 4 (RBOC4). Bit 5/BOC Bit 5 (RBOC5). Bit 6/This bit position is unused when BOCC.4 = 1.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode SR3 Status Register 3 18h 7 RAIS-CI 0 6 LOTC 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 X X X X X X X X Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a valid BOC. The setting of this bit prompts the user to read the RFDL register. Bit 1/Receive FDL Match Event (RMTCH).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode IMR3 Interrupt Mask Register 3 19h 7 RAIS-CI 0 6 LOTC 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 X X X X X X X X Bit 0/Receive BOC Detector Change-of-State Event (RBOC). 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive FDL Match Event (RMTCH). 0 = interrupt masked 1 = interrupt enabled Bit 2/TFDL Register Empty Event (TFDLE).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode SR4 Status Register 4 1Ah 7 — 0 6 RSA1 0 5 RSA0 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 X X X X X X X X Bit 0/Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Bit 1/Receive CRC4 Multiframe Event (RCMF).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode IMR4 Interrupt Mask Register 4 1Bh 7 — 0 6 RSA1 0 5 RSA0 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 X X X X X X X X Bit 0/Receive Align Frame Event (RAF). 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe Event (RCMF). 0 = interrupt masked 1 = interrupt enabled Bit 2/Receive Multiframe Event (RMF).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TFDL Transmit FDL Register 51h 7 TFDL7 0 6 TFDL6 0 5 TFDL5 0 4 TFDL4 0 3 TFDL3 0 2 TFDL2 0 1 TFDL1 0 0 TFDL0 0 0 0 0 1 1 1 0 0 Note: Also used to insert Fs framing pattern in D4 framing mode. The transmit FDL register (TFDL) contains the FDL information that is to be inserted on a byte-basis into the outgoing T1 data stream. The LSB is transmitted first.
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DS26502 T1/E1/J1/64KCC BITS Element 12. E1 SYNCHRONIZATION STATUS MESSAGE The DS26502 provides access to both the transmit and receive Sa/Si bits. In E1, the Sa bits are used to transmit and receive the SSM. The primary method to access the Sa (and Si) bits is based on CRC4 multiframe access. An alternate method is based on double-frame access. Table 12-1. E1 SSM Messages QUALITY LEVEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DESCRIPTION Quality unknown (existing sync network) Reserved Rec. G.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode RSiAF Receive Si Bits of the Align Frame 58h 7 SiF0 0 6 SiF2 0 5 SiF4 0 4 SiF6 0 3 SiF8 0 2 SiF10 0 1 SiF12 0 0 SiF14 0 X X X X X X X X Bit 0/Si Bit of Frame 14(SiF14). Bit 1/Si Bit of Frame 12(SiF12). Bit 2/Si Bit of Frame 10(SiF10). Bit 3/Si Bit of Frame 8(SiF8). Bit 4/Si Bit of Frame 6(SiF6). Bit 5/Si Bit of Frame 4(SiF4). Bit 6/Si Bit of Frame 2(SiF2).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode RRA Receive Remote Alarm 5Ah 7 RRAF1 0 6 RRAF3 0 5 RRAF5 0 4 RRAF7 0 3 RRAF9 0 2 RRAF11 0 1 RRAF13 0 0 RRAF15 0 X X X X X X X X Bit 0/Remote Alarm Bit of Frame 15(RRAF15). Bit 1/Remote Alarm Bit of Frame 13(RRAF13). Bit 2/Remote Alarm Bit of Frame 11(RRAF11). Bit 3/Remote Alarm Bit of Frame 9(RRAF9). Bit 4/Remote Alarm Bit of Frame 7(RRAF7).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode RSa5 Receive Sa5 Bits 5Ch 7 RSa5F1 0 6 RSa5F3 0 5 RSa5F5 0 4 RSa5F7 0 3 RSa5F9 0 2 RSa5F11 0 1 RSa5F13 0 0 RSa5F15 0 X X X X X X X X Bit 0/Sa5 Bit of Frame 15(RSa5F15). Bit 1/Sa5 Bit of Frame 13(RSa5F13). Bit 2/Sa5 Bit of Frame 11(RSa5F11). Bit 3/Sa5 Bit of Frame 9(RSa5F9). Bit 4/Sa5 Bit of Frame 7(RSa5F7). Bit 5/Sa5 Bit of Frame 5(RSa5F5).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode RSa7 Receive Sa7 Bits 5Eh 7 RSa7F1 0 6 RSa7F3 0 5 RSa7F5 0 4 RSa7F7 0 3 RSa7F9 0 2 RSa7F11 0 1 RSa7F13 0 0 RSa7F15 0 X X X X X X X X Bit 0/Sa7 Bit of Frame 15(RSa7F15). Bit 1/Sa7 Bit of Frame 13(RSa7F13). Bit 2/Sa7 Bit of Frame 11(RSa7F11). Bit 3/Sa7 Bit of Frame 9(RSa7F9). Bit 4/Sa7 Bit of Frame 7(RSa7F7). Bit 5/Sa7 Bit of Frame 5(RSa7F5). Bit 6/Sa7 Bit of Frame 3(RSa7F3).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TSiAF Transmit Si Bits of the Align Frame 42h 7 TsiF0 0 6 TsiF2 0 5 TsiF4 0 4 TsiF6 0 3 TsiF8 0 2 TsiF10 0 1 TsiF12 0 0 TsiF14 0 0 0 0 0 0 0 0 0 Bit 0/Si Bit of Frame 14(TsiF14). Bit 1/Si Bit of Frame 12(TsiF12). Bit 2/Si Bit of Frame 10(TsiF10). Bit 3/Si Bit of Frame 8(TsiF8). Bit 4/Si Bit of Frame 6(TsiF6). Bit 5/Si Bit of Frame 4(TsiF4). Bit 6/Si Bit of Frame 2(TsiF2).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TRA Transmit Remote Alarm 44h 7 TRAF1 0 6 TRAF3 0 5 TRAF5 0 4 TRAF7 0 3 TRAF9 0 2 TRAF11 0 1 TRAF13 0 0 TRAF15 0 0 0 0 0 0 0 0 0 Bit 0/Remote Alarm Bit of Frame 15(TRAF15). Bit 1/Remote Alarm Bit of Frame 13(TRAF13). Bit 2/Remote Alarm Bit of Frame 11(TRAF11). Bit 3/Remote Alarm Bit of Frame 9(TRAF9). Bit 4/Remote Alarm Bit of Frame 7(TRAF7).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TSa5 Transmit Sa5 Bits 46h 7 TSa5F1 0 6 TSa5F3 0 5 TSa5F5 0 4 TSa5F7 0 3 TSa5F9 0 2 TSa5F11 0 1 TSa5F13 0 0 TSa5F15 0 0 0 0 0 0 0 0 0 Bit 0/Sa5 Bit of Frame 15(TSa5F15). Bit 1/Sa5 Bit of Frame 13(TSa5F13). Bit 2/Sa5 Bit of Frame 11(TSa5F11). Bit 3/Sa5 Bit of Frame 9(TSa5F9). Bit 4/Sa5 Bit of Frame 7(TSa5F7). Bit 5/Sa5 Bit of Frame 5(TSa5F5).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TSa7 Transmit Sa7 Bits 48h 7 TSa7F1 0 6 TSa7F3 0 5 TSa7F5 0 4 TSa7F7 0 3 TSa7F9 0 2 TSa7F11 0 1 TSa7F13 0 0 TSa7F15 0 0 0 0 0 0 0 0 0 Bit 0/Sa7 Bit of Frame 15(TSa7F15). Bit 1/Sa7 Bit of Frame 13(TSa7F13). Bit 2/Sa7 Bit of Frame 11(TSa7F11). Bit 3/Sa7 Bit of Frame 9(TSa7F9). Bit 4/Sa7 Bit of Frame 7(TSa7F7). Bit 5/Sa7 Bit of Frame 5(TSa7F5).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TSACR Transmit Sa Bit Control Register 4Ah 7 SiAF 0 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 0 0 0 0 0 0 0 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8). 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream Bit 1/Additional Bit 7 Insertion Control Bit (Sa7).
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DS26502 T1/E1/J1/64KCC BITS Element 12.2 Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the receive align frame bit in status register 4 (SR4.0) will indicate that the contents of the RAF and RNAF have been updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: RNAF Receive Non-Align Frame Register 57h Bit # Name Default HW Mode 7 Si 0 6 1 0 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 X X X X X X X X Bit 0/Additional Bit 8 (Sa8). Bit 1/Additional Bit 7 (Sa7). Bit 2/Additional Bit 6 (Sa6). Bit 3/Additional Bit 5 (Sa5). Bit 4/Additional Bit 4 (Sa4). Bit 5 / Remote Alarm (A). Bit 6/Frame Nonalignment Signal Bit (1). In normal operation this bit will be = 1.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: TNAF Transmit Non-Align Frame Register 41h Bit # Name Default 6 1 1 7 Si 0 5 A 0 4 Sa4 0 3 Sa5 0 Bit 0/Additional Bit 8 (Sa8). Bit 1/Additional Bit 7 (Sa7). Bit 2/Additional Bit 6 (Sa6). Bit 3/Additional Bit 5 (Sa5). Bit 4/Additional Bit 4 (Sa4). Bit 5/Remote Alarm (used to transmit the alarm A). Bit 6/Frame Nonalignment Signal Bit (1). Bit 7/International Bit (Si).
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DS26502 T1/E1/J1/64KCC BITS Element 13. LINE INTERFACE UNIT (LIU) The LIU in the DS26502 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the network line; and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described below. The DS26502 can switch between T1 or E1 networks without changing any external components on either the transmit or receive side.
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DS26502 T1/E1/J1/64KCC BITS Element 13.1 LIU Operation The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer-coupled into the RTIP and RRING pins of the DS26502. The user has the option to use internal termination, software selectable for 75Ω/100Ω/110Ω/120Ω applications, or external termination. The LIU recovers clock and data from the analog signal and passes it through the jitter attenuation mux.
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DS26502 T1/E1/J1/64KCC BITS Element 13.2.2 Receive G.703 Section 10 Synchronization Signal The DS26502 can receive a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU G.703. To use the DS26502 in this mode, set the mode configuration bits in the Mode Configuration Register (MCREG). 13.2.3 Monitor Mode Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
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DS26502 T1/E1/J1/64KCC BITS Element The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode, the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the network load. See the Transmit Line Build-Out Control (TLBC) register for details. 13.3.
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DS26502 T1/E1/J1/64KCC BITS Element 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in Status Register 1 (SR1.4). 13.6 CMI (Code Mark Inversion) Option The DS26502 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B type of signal.
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DS26502 T1/E1/J1/64KCC BITS Element 13.7 LIU Control Registers Register Name: Register Description: Register Address: Bit # Name Default HW Mode 7 L2 0 L2 PIN 13 LIC1 Line Interface Control 1 30h 6 L1 0 L1 PIN 12 5 L0 0 L0 PIN 11 4 EGL 0 3 JAS 0 2 JABDS 0 1 DJA 0 0 TPD 0 0 0 0 0 1 Bit 0/Transmit Power-Down (TPD). 0 = powers down the transmitter and tri-states the TTIP and TRING pins 1 = normal transmitter operation Bit 1/Disable Jitter Attenuator (DJA).
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DS26502 T1/E1/J1/64KCC BITS Element T1 Mode L2 L1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 L0 0 1 0 1 0 1 0 1 APPLICATION DSX-1 (0 to 133 feet)/0dB CSU DSX-1 (133 to 266 feet) DSX-1 (266 to 399 feet) DSX-1 (399 to 533 feet) DSX-1 (533 to 655 feet) Reserved Reserved Reserved Register Name: Register Description: Register Address: Bit # Name Default HW Mode N (1) 1:2 1:2 1:2 1:2 1:2 RETURN LOSS N.M. N.M. N.M. N.M. N.M.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode LIC2 Line Interface Control 2 31h 7 — 0 6 LIRST 0 5 IBPV 0 0 0 0 4 TAIS 0 TAIS PIN 10 3 JACKS 0 JACKS PIN 46 2 RCCFE 0 1 SCLD 0 0 CLDS 0 0 0 0 Bit 0/Custom Line Driver Select (CLDS). Setting this bit to a one will redefine the operation of the transmit line driver. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode LIC3 Line Interface Control 3 32h 7 CMIE 0 6 CMII 0 5 — 0 4 MM1 0 3 MM0 0 2 — 0 1 — 0 0 TAOZ 0 0 0 0 0 0 0 0 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern at TTIP and TRING. 0 = disabled 1 = enabled Bit 1/Unused, must be set = 0 for proper operation. Bit 2/Unused, must be set = 0 for proper operation. Bits 3-4/Monitor Mode (MM0 to MM1).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode LIC4 Line Interface Control 4 33h 7 MPS1 0 MPS1 PIN 16 6 MPS0 0 MPS0 PIN 15 5 TT2 0 4 TT1 0 3 TT0 0 2 RT2 0 1 RT1 0 0 RT0 0 — — — — — — Bits 0-2/Receive Termination Select (RT0 to RT1).
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: INFO1 Information Register 1 11h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 — 0 3 RL3 0 2 RL2 0 1 RL1 0 0 RL0 0 X X X X X X X X Bits 0-3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RECEIVE LEVEL (dB) Greater than -2.5 -2.5 to -5.0 -5.0 to -7.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: SR1 Status Register 1 14h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 JALT 0 3 — 0 2 TCLE 0 1 TOCD 0 0 — 0 X X X X X X X X Bit 0/Unused, must be set = 0 for proper operation. Bit 1/Transmit Open Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are open-circuited. Note: This function not supported in transmit 6312kHz mode.
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DS26502 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: IMR1 Interrupt Mask Register 1 15h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 JALT 0 3 — 0 2 TCLE 0 1 TOCD 0 0 — 0 X X X X X X X X Bit 0/ Unused, must be set = 0 for proper operation. Bit 1/Transmit Open Circuit Detect Condition (TOCD). 0 = interrupt masked 1 = interrupt enabled–generates interrupts on rising and falling edges Bit 2/Transmit Current Limit Exceeded Condition (TCLE).
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DS26502 T1/E1/J1/64KCC BITS Element 13.8 Recommended Circuits Figure 13-4. Basic Interface VDD DS26502 2:1 TTIP TRANSMIT LINE C DVDD 0.1mF 0.01mF 0.1mF 10mF DVSS TRING TVDD + TVSS RVDD 1:1 RTIP 0.1mF RVSS RECEIVE LINE RRING R R 0.1mF NOTES: 1) 2) 3) All resistor values are ±1%. Resistors R should be set to 60W each if the internal receive-side termination feature is enabled. When this feature is disabled, R = 37.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 13-5. Protected Interface Using Internal Receive Termination VDD D1 D2 2:1 VDD DS26502 TTIP TRANSMIT LINE F1 S1 C1 0.1mF 0.01mF DVSS 0.1mF F2 DVDD D4 X2 D3 TRING TVDD 0.1mF 10mF + TVSS VDD D5 RVDD D6 0.1mF RVSS 1:1 RECEIVE LINE RTIP S2 F3 0.1mF D8 F4 X1 RRING D7 60 60 0.1mF NOTES: 1) All resistor values are ±1%. 2) X1 and X2 are very low DCR transformers 3) C1 = 10mF ceramic. 4) S1 and S2 are 6V transient suppressers.
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DS26502 T1/E1/J1/64KCC BITS Element 13.9 Component Specifications Table 13-1. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) ±2% 600mH minimum 1.0mH maximum 40pF maximum 1.0Ω maximum 2.0Ω maximum 1.2Ω maximum 1.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 13-6. E1 Transmit Pulse Template 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) Figure 13-7. T1 Transmit Pulse Template 1.2 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.8 0.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 13-8. Jitter Tolerance (T1 Mode) UNIT INTERVALS (UIpp) 1K DS26502 Tolerance 100 TR 62411 (Dec. 90) 10 ITU-T G.823 1 0.1 10 1 100 1K 10K 100K FREQUENCY (Hz) Figure 13-9. Jitter Tolerance (E1 Mode) UNIT INTERVALS (UIpp) 1k DS26502 Tolerance 100 40 10 1.5 1 0.1 Minimum Tolerance Level as per ITU G.823 1 10 20 100 1k FREQUENCY (Hz) 94 of 125 0.2 2.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 13-10. Jitter Attenuation (T1 Mode) -20dB r Cu ve A TR 62411 (Dec. 90) Prohibited Area -40dB rve Cu JITTER ATTENUATION (dB) 0dB B DS26502 T1 MODE -60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K JITTER ATTENUATION (dB) Figure 13-11. Jitter Attenuation (E1 Mode) 0dB ITU G.
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DS26502 T1/E1/J1/64KCC BITS Element 14. LOOPBACK CONFIGURATION Register Name: Register Description: Register Address: LBCR Loopback Control Register 20h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 — 0 3 LLB 0 0 0 0 0 0 2 RLB 0 RLB PIN 60 1 — 0 0 — 0 0 0 Bit 0/Unused, must be set = 0 for proper operation. Bit 1/Unused, must be set = 0 for proper operation. Bit 2/ Remote Loopback (RLB). In this loopback, data received at RTIP and RRING will be looped back to the transmit LIU.
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DS26502 T1/E1/J1/64KCC BITS Element 15. 64kHz SYNCHRONIZATION INTERFACE The 64kHz synchronization interface conforms to G.703 requirements for Centralized Timing (option A), Contradirectional Timing, and 64kHz Appendix II. It consists of a composite clock, where a 64kHz clock signal is generated or decoded, along with embedded frequencies of 8kHz and 400Hz. Those signals consist of AMI code with an 8kHz bipolar violation removed at every 400Hz.
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DS26502 T1/E1/J1/64KCC BITS Element 15.2 Transmit 64kHz Synchronization Interface Operation In the transmit path, the framer will generate the appropriate AMI waveform with the correct bipolar violations as described by G.703. If an 8kHz signal is present on the TS_8K_4 pin, the bipolar violations will be generated synchronously with this signal. If it is absent, the part will arbitrarily generate the bipolar violation at an 8kHz frequency. Table 15-2.
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DS26502 T1/E1/J1/64KCC BITS Element 16. 6312kHz SYNCHRONIZATION INTERFACE The DS26502 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix II.2 of G.703, with the exception that the DS26502 transmits a square wave as opposed to the sine wave that is defined in the G.703 specification. 16.1 Receive 6312kHz Synchronization Interface Operation On the receive interface, a 6312kHz sine wave is accepted conforming to the input port requirements of G.703 Appendix II.
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DS26502 T1/E1/J1/64KCC BITS Element 17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26502 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26502 contains the following as required by IEEE 1149.
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DS26502 T1/E1/J1/64KCC BITS Element TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 17-2. Test-Logic-Reset Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. Run-Test-Idle The run-test-idle is used between scan operations or during specific tests.
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DS26502 T1/E1/J1/64KCC BITS Element Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the test-logic-reset state.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 17-2.
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DS26502 T1/E1/J1/64KCC BITS Element 17.1 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage toward the serial output at JTDO.
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DS26502 T1/E1/J1/64KCC BITS Element IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During test-logic-reset, the identification code is forced into the instruction register’s parallel output.
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DS26502 T1/E1/J1/64KCC BITS Element Table 17-4.
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DS26502 T1/E1/J1/64KCC BITS Element CONTROL CELL CELL # NAME TYPE 28 TPOSO observe_only 29 TNEGO observe_only 30 TCLKO observe_only 31 TCLK observe_only 32 ALE_A7 observe_only 33 A6 observe_only 34 A5 observe_only 35 A4 observe_only 36 A3 observe_only 37 A2 observe_only 38 A1 observe_only 39 A0 observe_only 40 AD7 Output3 1 41 AD6 Output3 1 42 AD5 Output3 1 43 AD4 Output3 1 44 AD3 Output3 1 45 AD2 Output3 1 107 of 125
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DS26502 T1/E1/J1/64KCC BITS Element 18. FUNCTIONAL TIMING DIAGRAMS 18.1 Processor Interface 18.1.1 Parallel Port Mode See the AC Timing section. 18.1.2 SPI Serial Port Mode Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 SCK CS MOSI 1 0 0 0 0 0 0 MSB A7 A6 LSB MSB A5 A4 A3 A2 A1 A0 B LSB MISO D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB Figure 18-2.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 SCK CS MOSI 1 0 0 0 0 0 0 MSB A7 A6 LSB MSB A5 A4 A3 A2 A1 A0 B LSB MISO D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 SCK CS MOSI 0 0 0 0 0 0 0 MSB A7 LSB A6 A5 A4 A3 A2 A1 A0 MSB B D7 LSB MSB D6 D5 D4 D3 D2 D1 MISO Figure 18-6.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 SCK CS MOSI 0 0 0 0 0 0 0 A7 MSB A6 A5 A4 A3 A2 A1 A0 D7 B D6 D5 D4 D3 D2 D1 LSB MSB LSB MSB D0 LSB MISO Figure 18-8.
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DS26502 T1/E1/J1/64KCC BITS Element 19. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS26502L…………………………………………………………0°C to +70°C Operating Temperature Range for DS26502LN……………………………………………………..-40°C to +85°C Storage Temperature Range………………………………………………………………………...-55°C to +125°C Soldering Temperature…………………………………………………...
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DS26502 T1/E1/J1/64KCC BITS Element Table 19-5. DC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26502L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26502LN.) PARAMETER SYMBOL MIN TYP MAX UNITS 85 150 mA +1.0 mA 5 1.0 mA 6 Supply Current IDD Input Leakage IIL Output Leakage ILO Output Current (2.4V) IOH -1.0 mA Output Current (0.4V) IOL +4.0 mA Note 5: Note 6: -1.0 0.0V < VIN < VDD Applied to INT when tri-stated.
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DS26502 T1/E1/J1/64KCC BITS Element 20. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals and 20pF for all others. 20.1 Multiplexed Bus Table 20-1. AC Characteristics, Multiplexed Parallel Port (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26502L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26502LN.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) t CYC ALE WR PWASH t ASD t ASD t ASED RD PWEL PWEH t CH t CS CS t ASL t DHR t DDR AD0-AD7 t AHL Figure 20-2.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 20-3.
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DS26502 T1/E1/J1/64KCC BITS Element 20.2 Nonmultiplexed Bus Table 20-2. AC Characteristics, Non-Mux Parallel Port (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26502L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26502LN.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01) A0 to A7 Address Valid D0 to D7 Data Valid t5 5ns min/20ns max WR t1 0ns min CS 0ns min t2 t3 t4 75ns max RD 0ns min Figure 20-5.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) A0 to A7 Address Valid D0 to D7 Data Valid 5ns min. / 20ns max. t5 R/W t1 CS 0ns min. 0ns min. t2 t3 t4 0ns min. 75ns max. DS Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01) A0 to A7 Address Valid D0 to D7 10ns min. R/W t1 t7 t8 10ns min. 0ns min. CS 0ns min. DS t2 t6 75ns min. 118 of 125 t4 0ns min.
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DS26502 T1/E1/J1/64KCC BITS Element 20.3 Serial Bus Table 20-3. AC Characteristics, Serial Bus (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26502L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26502LN.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 CS INPUT 1 3 5 CLK INPUT CPOL = 0 4 2 CLK INPUT CPOL = 1 5 4 8 9 MISO INPUT SLAVE MSB 6 MOSI OUTPUT BITS 6-1 BITS 6-1 MSB NOTE 11 10 7 SLAVE LSB 11 LSB Note: Not defined, but usually MSB of character just received. Figure 20-9.
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DS26502 T1/E1/J1/64KCC BITS Element 20.4 Receive Side AC Characteristics Table 20-4. Receive Side AC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26502L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26502LN.) PARAMETER RCLK Period SYMBOL RCLK to RSER Delay RCLK to RS_8K, 400Hz Delay tD2 RCLK Pulse Width TYP MAX UNITS NOTES 1 2 5 6 3 3 5 5 4 4 5 5 20 ns ns ms ns ns ns ms ms ns ns ms ms ns 50 ns 488 648 15.6 158.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 20-10. Receive Timing, T1, E1, 64KCC Mode RCLK t D1 RSER t D2 E1 = MSB of Channel 1 T1 = F-Bit RS_8K1 t D2 RS_8K2 t D2 400HZ3 NOTES: 1) RS_8K output in T1 or E1 mode. 2) RS_8K output in 64KCC mode. 3) 400Hz output active only in 64KCC mode, high impedance in all other modes.
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DS26502 T1/E1/J1/64KCC BITS Element 20.5 Transmit Side AC Characteristics Table 20-5. Transmit Side AC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85°C.) PARAMETER SYMBOL TCLK Period tCP TCLK Pulse Width tCH tCL TCLK Rise and Fall Times tSU Delay TCLK to TS_8K_4 tD2 Delay TCLKO to TPOSO and TNEGO tDD E1 mode. Note 2: T1 or J1 mode. Note 3: 64KCC mode. Note 4: 6312kHz mode. Note 5: TS_8K_4 in input mode. Note 6: TS_8K_4 in output mode. TYP 488 648 15.6 158.
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DS26502 T1/E1/J1/64KCC BITS Element Figure 20-11. Transmit Timing, T1, E1, 64KCC Mode t CP t CL tF tR TCLK t SU TSER t HD t D2 TS_8K_41 t SU TS_8K_42 TCLKO TPOSO, TNEGO t DD NOTES: 1) TS_8K_4 in output mode. 2) TS_8K_4 in input mode. 21. REVISION HISTORY REVISION 070904 DESCRIPTION New product release.
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DS26502 T1/E1/J1/64KCC BITS Element 22. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) 125 of 125 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied.