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DS2182A

T1 Line Monitor

DS218A

041995 1/22

FEATURES

• Performs framing and monitoring functions

• Supports Superframe and Extended Superframe

formats

• Four onboard error counters

– 16-bit bipolar violation

– 8-bit CRC

– 8-bit OOF

– 8-bit frame bit error

• Indication of the following

– yellow and blue alarms

– incoming B8ZS code words

– 8 and 16 zero strings

– change of frame alignment

– loss of sync

– carrier loss

• Simple serial interface used for configuration, control

and status monitoring

• Burst mode allows quick access to counters for status

updates

• Automatic counter reset feature

• Single 5V supply; low-power CMOS technology

• Available in 28-pin DIP and 28-pin PLCC

• The DS2182A is upward-compatible from the original

DS2182

PIN ASSIGNMENT

14 15

28-Pin DIP (600 MIL)

INT

SDI

SDO

SCLK

RYEL

RLINK

RLCLK

RCLK

RCHCLK

RSER

VSS

VDD

RLOS

RFER

RBV

RCL

RNEG

RPOS

RST

TEST

RSIGSEL

RSIGFR

RABCD

RMSYNC

RFSYNC

The updated DS2182A includes the following changes

from the original DS2182:

• ability to count excessive zeros

• Severely Errored Framing Event indication

• updated AIS detection

• updated RCL detection

• AIS and RCL alarm clear indications

DESCRIPTION

The DS2182A T1 Line Monitor Chip is a monolithic

CMOS device designed to monitor real-time perform-

ance on T1 lines. The DS2182A frames to the data on

the line, counts errors, and supplies detailed informa-

tion about the status and condition of the line. Large on-

board counters allow the accumulation of errors for ex-

tended periods, which permits a single CPU to monitor a

number of T1 lines. Output clocks that are synchronized

to the incoming data stream are provided for easy ex-

traction of S-Bits, FDL bits, signaling bits, and channel

data. The DS2182A meets the requirements of ANSI

T1.231.

Summary of content (22 pages)

PAGE 1
DS218A DS2182A T1 Line Monitor FEATURES • Performs framing and monitoring functions • Supports Superframe and Extended Superframe formats • Four onboard error counters – – – – 16-bit bipolar violation 8-bit CRC 8-bit OOF 8-bit frame bit error • Indication of the following – – – – – – yellow and blue alarms incoming B8ZS code words 8 and 16 zero strings change of frame alignment loss of sync carrier loss • Simple serial interface used for configuration, control and status monitoring • Burst mode a
PAGE 2
DS2182A DS2182A BLOCK DIAGRAM Figure 1 CS SCLK SDI RST SERIAL PORT INTERFACE TEST INFORMATION REGISTERS VDD VSS INT SDO RLOS RYEL YELLOW ALARM DETECT RCL RECEIVE SYNC CONTROLLER RBV BIPOLAR DECODER RPOS RNEG RSER RABCD DATA DEMUX RLINK RLCLK RCLK RSIGFR RSIGSEL RCHCLK RECEIVE TIMING CRC RMSYNC RFSYNC 041995 2/22 SYNCHRONIZER RFER
PAGE 3
DS2182A PIN DESCRIPTION Table 1 PIN SYMBOL TYPE DESCRIPTION 6 NC – No Connect. No internal connection. This pin can be tied to either VSS or VDD, or it can be floated. 7 RYEL O Receive Yellow Alarm. Transitions high when yellow alarm detected; goes low when alarm clears. 8 RLINK O Receive Link Data. Updated with extracted FDL data one RCLK before start of odd frames (193E) and held until next update.
PAGE 4
DS2182A PORT PIN DESCRIPTION Table 2 PIN SYMBOL TYPE DESCRIPTION 1 INT O Receive Alarm Interrupt. Flags host controller during alarm conditions. Active low; open drain output. 2 SDI I Serial Data In. Data for onboard registers. Sampled on rising edge of SCLK. 3 SDO O Serial Data Out. Control and status information from onboard registers. Updated on falling edge of SCLK; tri-stated during serial port write or when CS is high. 4 CS I Chip Select.
PAGE 5
DS2182A SERIAL PORT INTERFACE The port pins of the DS2182A serve as a microprocessor/microcontroller-compatible serial port. Eleven onboard registers allow the user to update operational characteristics and monitor device status via a host controller, minimizing hardware interfaces. The port on the DS2182A can be read from or written to at any time. Serial port reads and writes are independent of T1 line timing signals RCLK, RPOS, and RNEG.
PAGE 6
DS2182A SERIAL PORT READ/WRITE Figure 3 CS SCLK SDI SDO R/W A0 A1 A2 A3 0 0 BM D0 D1 ADDRESS/COMMAND D2 D3 D4 D5 D6 D7 DATA INPUT/OUTPUT NOTES: 1. SDI is sampled on rising edge of SCLK. 2. SDO is updated on falling edge of SCLK. OPERATION OF THE COUNTERS All four of the counters in the DS2182A can be preset by the user to establish an event count interrupt threshold. The counters count up from the preset value until they reach saturation.
PAGE 7
DS2182A CRCCR: CRC COUNT REGISTER Figure 5 (MSB) CRC7 (LSB) CRC6 CRC5 CRC4 CRC3 SYMBOL POSITION NAME AND DESCRIPTION CRC7 CRCCR.7 MSB of CRC6 word error count CRC0 CRCCR.0 LSB of CRC6 word error count The CRC Count Register (CRCCR) is an 8-bit presettable counter that records word errors in the Cyclic Redundancy Check (CRC). This 8-bit binary counter saturates at 255 and generates an interrupt for each occurrence after saturation if RIMR2.1 is set.
PAGE 8
DS2182A RSR1: RECEIVE STATUS REGISTER 1 Figure 8 (MSB) 8ZD (LSB) 16ZD RCL RYEL RLOS B8ZSD RBL COFA SYMBOL POSITION NAME AND DESCRIPTION 8ZD RSR1.7 8 Zero Detect. Set when a string of eight consecutive 0s has been received at RPOS and RNEG. 16ZD RSR1.6 16 Zero Detect. Set when a string of 16 consecutive 0s has been received at RPOS and RNEG. RCL RSR1.5 Receive Carrier Loss. Set when a string of 192 consecutive 0s has been received at RPOS and RNEG.
PAGE 9
DS2182A RIMR1: RECEIVE INTERRUPT MASK REGISTER 1 Figure 9 (MSB) 8ZD (LSB) 16ZD RCL RYEL RLOS B8ZSD SYMBOL POSITION 8ZD RIMR1.7 8 Zero Detect Mask. 1 = interrupt enabled 0 = interrupt masked 16ZD RIMR1.6 16 Zero Detect Mask. 1 = interrupt enabled 0 = interrupt masked RCL RIMR1.5 Receive Carrier Loss Mask. 1 = interrupt enabled 0 = interrupt masked RYEL RIMR1.4 Receive Yellow Alarm Mask. 1 = interrupt enabled 0 = interrupt masked RLOS RIMR1.3 Receive Loss Of Sync Mask.
PAGE 10
DS2182A RSR2: RECEIVE STATUS REGISTER 2 Figure 10 (MSB) SEFE (LSB) RCLC RBLC FERR FECS OOFCS CRCCS BPVCS SYMBOL POSITION NAME AND DESCRIPTION SEFE RSR2.7 Severely Errored Framing Event. Set when 2 out of 6 framing bits (Ft or FPS) are received in error. RCLC RSR2.6 Receive Carrier Loss Clear. Set when the carrier signal is restored; will remain set until read. RBLC RSR2.5 Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no longer detected; will remain set until read.
PAGE 11
DS2182A CRCCS RIMR2.1 CRC Count Saturation Mask. 1 = interrupt enabled 0 = interrupt masked BPVCS RIMR2.0 Bipolar Violation Count Saturation Mask. 1 = interrupt enabled 0 = interrupt masked RCR1: RECEIVE CONTROL REGISTER 1 Figure 12 (MSB) ARC (LSB) OOF1 OOF2 ACR SYNCC SYNCT SYNCE RESYNC SYMBOL POSITION NAME AND DESCRIPTION ARC RCR1.7 Auto Resync Criteria. 1 = resync on OOF event only 0 = resync on OOF event or Receive Carrier Loss (RCL) OOF1 RCR1.6 Out Of Frame 1.
PAGE 12
DS2182A SYNC CRITERIA (RCR1.3) 193E. Bit RCR1.3 determines which sync algorithm is utilized when resync is in progress (RLOS = 1). In 193E framing, when RCR1.3 = 0, the synchronizer will lock only to the FPS pattern and will move to the new frame and multiframe alignment after the framing candidate is qualified. RLOS will go low one frame after the move to the new alignment. When RCR1.3 = 1, the new alignment is further tested by a CRC6 code match. RLOS will transition low after a CRC6 match occurs.
PAGE 13
DS2182A RCR2: RECEIVE CONTROL REGISTER 2 Figure 13 (MSB) (LSB) – – BVCRF FM SFYEL B8ZS – – SYMBOL POSITION NAME AND DESCRIPTION - RCR2.7 Reserved; must be 0 for proper operation. - RCR2.6 Reserved; must be 0 for proper operation. BVCRF RCR2.5 Bipolar Violation Count Register Function Select. 0 = do not count excessive zeros 1 = count excessive zeros FM RCR2.4 Frame Mode. 1 = Extended Superframe (193E, 24 frames per Superframe). 0 = Superframe (193S or D4, 12 frames per Superframe).
PAGE 14
DS2182A 193E RECEIVE MULTIFRAME TIMING Figure 15 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RFSYNC RMSYNC RSIGSEL RSIGFR RLCLK RABCD ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ D A B C D RLINK NOTES: 1. Signaling data is updated during signaling frames on channel boundaries. Pin RABCD is the LSB of each channel word in non-signaling frames. 2. RLINK data (FDL data) is updated one bit-time prior to odd frames and held for two frames.
PAGE 15
DS2182A RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16 RCLK CHANNEL 1 CHANNEL 2 RPOS, RNEG LSB F LSB MSB MSB LSB MSB RFSYNC RMSYNC RSIGSEL RSIGFR RLCLK RCHCLK RLINK RABCD CHANNEL 23 CHANNEL 24 CHANNEL 1 RSER LSB MSB LSB F MSB NOTES: 1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held across multiframe edges. 2. Total delay from RPOS and RNEG to RSER output is 13 RCLK periods.
PAGE 16
DS2182A RBV OUTPUT The bipolar violation output transitions high when the accused bit emerges at RSER. RBV goes low at the next bit time if no additional violations are detected. RFER OUTPUT The receive frame error output transitions high at the Fbit time and is held high for two bit periods when a frame bit error occurs. In 193S, framing FT and FS patterns are tested. The FPS pattern is tested in 193E framing.
PAGE 17
DS2182A ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -1.0V to 7.0V 0°C to +70°C -55°C to 125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 18
DS2182A CHARACTERISTICS1,2 SERIAL PORT PARAMETER (0°C to 70°C; VDD = 5V + 10%) SYMBOL MIN TYP MAX SDI to SCLK Setup tDC 50 ns SCLK to SDI Hold tCDH 50 ns SDI to SCLK Falling Edge tCD 50 ns SCLK Low Time tCL 250 ns SCLK High Time tCH 250 ns SCLK Rise and Fall Times tR,tF CS to SCLK Setup tCC 50 ns SCLK to CS hold tCCH 50 ns CS Inactive Time tCWH 2.5 µs SCLK to SDO Valid tCDV 200 ns CS to SDO High Z tCDZ 75 ns 100 UNITS NOTES ns NOTES: 1.
PAGE 19
DS2182A SERIAL PORT WRITE AC TIMING DIAGRAM Figure 18 tCWH tCC CS tSCC tCH tF tR ÇÇ ÇÇ ÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉ ÉÉ tCCH SCLK tDC SDI tCDH tCL tCD tCDH LSB1 LSB CONTROL BYTE MSB DATA BYTE ÉÉÉ ÉÉÉ NOTES: 1. Data byte bits must be valid across low clock periods to prevent transients in operating modes. 2. Shaded regions indicate don’t-care states of input. SERIAL PORT READ1 AC TIMING DIAGRAM Figure 19 CS tCDZ SCLK tCDV SDO High Z NOTE: 1.
PAGE 20
DS2182A RECEIVE AC TIMING DIAGRAM Figure 20 tP tWL RCLK tPRD RSER, RABCD, RLINK tPRS RMSYNC, RFSYNC RSIGSEL, RSIGFR RLCLK, RCHCLK tPRA RYEL, RCL, RBV RFER, RLOS tRST RST tSRD RPOS, RNEG 041995 20/22 tHRD tWH tF tR
PAGE 21
DS2182A DS2182A T1 LINE MONITOR 28-PIN DIP 28 15 B 14 1 A D C J E K G F H 13 EQUAL SPACES AT + .010 TNA INCHES DIM MIN MAX A 1.445 1.470 B 0.530 0.550 C 0.140 0.160 D 0.600 0.625 E 0.015 0.040 F 0.120 0.145 G 0.090 0.110 H 0.600 0.680 J 0.008 0.012 K 0.015 0.
PAGE 22
DS2182A DS2182AQ T1 LINE MONITOR 28-PIN PLCC E E1 B L1 N 1 D1 D D2 B1 CH1 e1 C E2 A2 INCHES DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 - B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 D 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 0.390 0.430 L1 0.060 - N 28 - e1 CH1 041995 22/22 0.050 BSC 0.042 0.