User guide

DS2181A

041995 12/32

TSD INPUT TIMING (TCR.6 = 1; TCR.5 = 0) Table 6

FRAME # TIMESLOT SIGNALLING

DATA SAMPLED AT TSD

0 17

1 1,18

2 2,19

3 3,20

4 4,21

5 5,22

6 6,23

7 7,24

8 8,25

9 9,26

10 0,27

11 11,28

12 12,29

13 13,30

14 14,31

15 15

NOTE:

1. A, B, C and D data is sampled on falling edges of TCLK during bit times 5, 6, 7 and 8 of timeslots indicated.

TSD INPUT TIMING Figure 7

SAMPLED

FOR TIMESLOT 1

TCLK

TCHCLK

TSD

DON’T CARE DON’T CAREAB DCABDC

FRAME 1

TIMESLOT 1 TIMESLOT 18

SAMPLED

FOR TIMESLOT 18